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Commit 3e72771e authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Stephen Warren
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clk: tegra: move from a lock bit idx to a lock mask



PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 0b6525ac
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