Commit 3dd065e7 authored Jul 25, 2017 by Peter De Schrijver Committed by Stephen Boyd Aug 23, 2017

clk: tegra: change post IDDQ release delay to 5us



Increase delay after PLL IDDQ release to 5us per PLL specifications.

based on work by Alex Frid <afrid@nvidia.com>

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

parent 82c875ca

drivers/clk/tegra/clk-pll.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -363,7 +363,7 @@ static void _clk_pll_enable(struct clk_hw *hw)
		val = pll_readl(pll->params->iddq_reg, pll);
		val &= ~BIT(pll->params->iddq_bit_idx);
		pll_writel(val, pll->params->iddq_reg, pll);
		udelay(2);
		udelay(5);
		}

		if (pll->params->reset_reg) {