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Commit 3c86f3f6 authored by Ritesh Harjani's avatar Ritesh Harjani Committed by Ram Prakash Gupta
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mmc: sdhci-msm: Add CQHCI support for sdhci-msm 



This change is part of mmc driver porting to enable command
queue.

mmc: cqhci: Move CQHCI_ENABLE before setting TDLBA/TDLBAU
Without this patch the CQHCI registers are getting reset
again.

This adds CQHCI support for sdhci-msm platforms.
mmc: sdhci-msm: Change the desc_sz on cqe_enable/disable.

When CMDQ is halted the HW expects descriptor size to
be same which is using in CMDQ mode.
Thus adjust the desc_sz of sdhci accordingly.

Without this patch below command gives ADMA error
when CQE is enabled.
cat /sys/kernel/debug/mmc0/mmc0:0001/ext_csd

mmc: sdhci-msm: Handle unexpected interrupt case on CQE halt

There is a case when enabling the legacy IRQs and halting CQE is
resuling into a command response interrupt without any command in
progress. This patch handles such case here.

Error signature without this patch:-
mmc0: Got command interrupt 0x00000001 even though no command operation
was in progress.

Change-Id: I7f278d4547b7aa26590a1b60258b0f567a126893
Signed-off-by: default avatarRitesh Harjani <riteshh@codeaurora.org>
Signed-off-by: default avatarRam Prakash Gupta <rampraka@codeaurora.org>
parent 74f401c2

drivers/mmc/host/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -454,6 +454,7 @@ config MMC_SDHCI_MSM 
	depends on ARCH_QCOM || (ARM && COMPILE_TEST)

	depends on MMC_SDHCI_PLTFM

	select MMC_SDHCI_IO_ACCESSORS

	select MMC_CQHCI

	help

	  This selects the Secure Digital Host Controller Interface (SDHCI)

	  support present in Qualcomm Technologies, Inc. SOCs. The controller

drivers/mmc/host/cqhci.c

+6 −14
Original line number Diff line number Diff line 
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2015, 2019, The Linux Foundation.

 * All rights reserved.

 */



#include <linux/delay.h>
@@ -267,6 +260,9 @@ static void __cqhci_enable(struct cqhci_host *cq_host) 


	cqhci_writel(cq_host, cqcfg, CQHCI_CFG);



	cqcfg |= CQHCI_ENABLE;

	cqhci_writel(cq_host, cqcfg, CQHCI_CFG);



	cqhci_writel(cq_host, lower_32_bits(cq_host->desc_dma_base),

		     CQHCI_TDLBA);

	cqhci_writel(cq_host, upper_32_bits(cq_host->desc_dma_base),
@@ -276,10 +272,6 @@ static void __cqhci_enable(struct cqhci_host *cq_host) 


	cqhci_set_irqs(cq_host, 0);



	cqcfg |= CQHCI_ENABLE;



	cqhci_writel(cq_host, cqcfg, CQHCI_CFG);



	mmc->cqe_on = true;



	if (cq_host->ops->enable)

drivers/mmc/host/sdhci-msm.c

+122 −1
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ 
#include <trace/events/mmc.h>



#include "sdhci-msm.h"

#include "sdhci-pltfm.h"

#include "cqhci.h"



#define QOS_REMOVE_DELAY_MS	10

#define CORE_POWER		0x0
@@ -2200,6 +2202,117 @@ static void sdhci_msm_bus_work(struct work_struct *work) 
	spin_unlock_irqrestore(&host->lock, flags);

}



/*****************************************************************************\

 *                                                                           *

 * MSM Command Queue Engine (CQE)                                            *

 *                                                                           *

\*****************************************************************************/



static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)

{

	int cmd_error = 0;

	int data_error = 0;



	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))

		return intmask;



	cqhci_irq(host->mmc, intmask, cmd_error, data_error);

	return 0;

}



void sdhci_msm_cqe_enable(struct mmc_host *mmc)

{

	struct sdhci_host *host = mmc_priv(mmc);



	if (host->flags & SDHCI_USE_64_BIT_DMA)

		host->desc_sz = 12;



	sdhci_cqe_enable(mmc);

}



void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)

{

	struct sdhci_host *host = mmc_priv(mmc);

	unsigned long flags;

	u32 ctrl;



	if (host->flags & SDHCI_USE_64_BIT_DMA)

		host->desc_sz = 16;



	spin_lock_irqsave(&host->lock, flags);



	ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);

	ctrl |= SDHCI_INT_RESPONSE;

	sdhci_writel(host,  ctrl, SDHCI_INT_ENABLE);

	sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);



	spin_unlock_irqrestore(&host->lock, flags);



	sdhci_cqe_disable(mmc, recovery);

}



static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {

	.enable		= sdhci_msm_cqe_enable,

	.disable	= sdhci_msm_cqe_disable,

};



#ifdef CONFIG_MMC_CQHCI

static int sdhci_msm_cqe_add_host(struct sdhci_host *host,

				struct platform_device *pdev)

{

	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	struct sdhci_msm_host *msm_host = pltfm_host->priv;

	struct cqhci_host *cq_host;

	bool dma64;

	int ret;



	ret = sdhci_setup_host(host);

	if (ret)

		return ret;



	cq_host = cqhci_pltfm_init(pdev);

	if (IS_ERR(cq_host)) {

		ret = PTR_ERR(cq_host);

		dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);

		goto cleanup;

	}



	msm_host->mmc->caps2 |= MMC_CAP2_CQE;

	cq_host->ops = &sdhci_msm_cqhci_ops;



	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;

	if (dma64)

		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;



	ret = cqhci_init(cq_host, host->mmc, dma64);

	if (ret) {

		dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",

					mmc_hostname(host->mmc),

					ret);

		goto cleanup;

	}



	ret = __sdhci_add_host(host);

	if (ret)

		goto cleanup;



	dev_info(&pdev->dev, "%s: CQE init: success\n",

					mmc_hostname(host->mmc));

	return ret;



cleanup:

	sdhci_cleanup_host(host);

	return ret;

}

#else

static void sdhci_msm_cqe_add_host(struct sdhci_host *host,

				struct platform_device *pdev)

{

	dev_warn(&pdev->dev, "CQE config not enabled, defaulting to sdhci\n");

	return sdhci_add_host(host);

}

#endif /* CONFIG_MMC_CQHCI */



/*

 * This function cancels any scheduled delayed work and sets the bus

 * vote based on bw (bandwidth) argument.
@@ -4382,6 +4495,7 @@ static struct sdhci_ops sdhci_msm_ops = { 
	.post_req = sdhci_msm_post_req,

	.get_current_limit = sdhci_msm_get_current_limit,

	.notify_load = sdhci_msm_notify_load,

	.irq = sdhci_msm_cqe_irq,

};



static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host,
@@ -4522,6 +4636,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) 
	struct sdhci_pltfm_host *pltfm_host;

	struct sdhci_msm_host *msm_host;

	struct resource *core_memres = NULL;

	struct device_node *node = pdev->dev.of_node;

	int ret = 0, dead = 0;

	u16 host_version;

	u32 irq_status, irq_ctl;
@@ -4928,7 +5043,12 @@ static int sdhci_msm_probe(struct platform_device *pdev) 
		}

	}



	if (of_device_is_compatible(node, "qcom,sdhci-msm-cqe")) {

		dev_dbg(&pdev->dev, "node with qcom,sdhci-msm-cqe\n");

		ret = sdhci_msm_cqe_add_host(host, pdev);

	} else {

		ret = sdhci_add_host(host);

	}

	if (ret) {

		dev_err(&pdev->dev, "Add host failed (%d)\n", ret);

		goto vreg_deinit;
@@ -5267,6 +5387,7 @@ static const struct dev_pm_ops sdhci_msm_pmops = { 
static const struct of_device_id sdhci_msm_dt_match[] = {

	{.compatible = "qcom,sdhci-msm"},

	{.compatible = "qcom,sdhci-msm-v5"},

	{.compatible = "qcom,sdhci-msm-cqe"},

	{},

};

MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);