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Commit 3ad8a208 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Fix up cpt pixel multiplier enable sequence 



Bspec for the "DPLL HDMI multiplier" field says:

"Restriction : The DPLL must be enabled and stable before setting these bits.
These bits must be programmed after DPLL_SEL is programmed."

There is apparently no restriction on programming the DPLL_SEL
register wrt the DPLL. So let's just move that up before we enable the
pch dpll.

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 426115cf

drivers/gpu/drm/i915/intel_display.c

+11 −9
Original line number Original line Diff line number Diff line
@@ -3004,15 +3004,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 
	/* For PCH output, training FDI link */

	/* For PCH output, training FDI link */

	dev_priv->display.fdi_link_train(crtc);

	dev_priv->display.fdi_link_train(crtc);





	/* XXX: pch pll's can be enabled any time before we enable the PCH

	/* We need to program the right clock selection before writing the pixel

	 * transcoder, and we actually should do this to not upset any PCH

	 * mutliplier into the DPLL. */

	 * transcoder that already use the clock when we share it.

	 *

	 * Note that enable_shared_dpll tries to do the right thing, but

	 * get_shared_dpll unconditionally resets the pll - we need that to have

	 * the right LVDS enable sequence. */

	ironlake_enable_shared_dpll(intel_crtc);



	if (HAS_PCH_CPT(dev)) {

	if (HAS_PCH_CPT(dev)) {

		u32 sel;

		u32 sel;
@@ -3026,6 +3019,15 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 
		I915_WRITE(PCH_DPLL_SEL, temp);

		I915_WRITE(PCH_DPLL_SEL, temp);

	}

	}





	/* XXX: pch pll's can be enabled any time before we enable the PCH

	 * transcoder, and we actually should do this to not upset any PCH

	 * transcoder that already use the clock when we share it.

	 *

	 * Note that enable_shared_dpll tries to do the right thing, but

	 * get_shared_dpll unconditionally resets the pll - we need that to have

	 * the right LVDS enable sequence. */

	ironlake_enable_shared_dpll(intel_crtc);



	/* set transcoder timing, panel must allow it */

	/* set transcoder timing, panel must allow it */

	assert_panel_unlocked(dev_priv, pipe);

	assert_panel_unlocked(dev_priv, pipe);

	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);

	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);