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Commit 426115cf authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence 



No need to call the ->pre_pll_enable hook twice if we don't enable the
dpll too early. This should make Jani a bit less grumpy.

v2: Rebase on top of the newly-colored BUG_ONs.

v3: Reinstate the lost write of the DPLL_MD register, spotted by Imre.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 84734a04

drivers/gpu/drm/i915/intel_display.c

+20 −27
Original line number Original line Diff line number Diff line
@@ -1321,32 +1321,40 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);

	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);

}

}





static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)

static void vlv_enable_pll(struct intel_crtc *crtc)

{

{

	int reg;

	struct drm_device *dev = crtc->base.dev;

	u32 val;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int reg = DPLL(crtc->pipe);

	u32 dpll = crtc->config.dpll_hw_state.dpll;





	assert_pipe_disabled(dev_priv, pipe);

	assert_pipe_disabled(dev_priv, crtc->pipe);





	/* No really, not for ILK+ */

	/* No really, not for ILK+ */

	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));

	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));





	/* PLL is protected by panel, make sure we can write it */

	/* PLL is protected by panel, make sure we can write it */

	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))

	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))

		assert_panel_unlocked(dev_priv, pipe);

		assert_panel_unlocked(dev_priv, crtc->pipe);





	reg = DPLL(pipe);

	I915_WRITE(reg, dpll);

	val = I915_READ(reg);

	POSTING_READ(reg);

	val |= DPLL_VCO_ENABLE;

	udelay(150);



	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))

		DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);



	I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);

	POSTING_READ(DPLL_MD(crtc->pipe));





	/* We do this three times for luck */

	/* We do this three times for luck */

	I915_WRITE(reg, val);

	I915_WRITE(reg, dpll);

	POSTING_READ(reg);

	POSTING_READ(reg);

	udelay(150); /* wait for warmup */

	udelay(150); /* wait for warmup */

	I915_WRITE(reg, val);

	I915_WRITE(reg, dpll);

	POSTING_READ(reg);

	POSTING_READ(reg);

	udelay(150); /* wait for warmup */

	udelay(150); /* wait for warmup */

	I915_WRITE(reg, val);

	I915_WRITE(reg, dpll);

	POSTING_READ(reg);

	POSTING_READ(reg);

	udelay(150); /* wait for warmup */

	udelay(150); /* wait for warmup */

}

}
@@ -3654,7 +3662,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 
		if (encoder->pre_pll_enable)

		if (encoder->pre_pll_enable)

			encoder->pre_pll_enable(encoder);

			encoder->pre_pll_enable(encoder);





	vlv_enable_pll(dev_priv, pipe);

	vlv_enable_pll(intel_crtc);





	for_each_encoder_on_crtc(dev, crtc, encoder)

	for_each_encoder_on_crtc(dev, crtc, encoder)

		if (encoder->pre_enable)

		if (encoder->pre_enable)
@@ -4409,7 +4417,6 @@ static void vlv_update_pll(struct intel_crtc *crtc) 
{

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_encoder *encoder;

	int pipe = crtc->pipe;

	int pipe = crtc->pipe;

	u32 dpll, mdiv;

	u32 dpll, mdiv;

	u32 bestn, bestm1, bestm2, bestp1, bestp2;

	u32 bestn, bestm1, bestm2, bestp1, bestp2;
@@ -4498,10 +4505,6 @@ static void vlv_update_pll(struct intel_crtc *crtc) 




	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);

	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);





	for_each_encoder_on_crtc(dev, &crtc->base, encoder)

		if (encoder->pre_pll_enable)

			encoder->pre_pll_enable(encoder);



	/* Enable DPIO clock input */

	/* Enable DPIO clock input */

	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |

	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |

		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;

		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
@@ -4511,20 +4514,10 @@ static void vlv_update_pll(struct intel_crtc *crtc) 
	dpll |= DPLL_VCO_ENABLE;

	dpll |= DPLL_VCO_ENABLE;

	crtc->config.dpll_hw_state.dpll = dpll;

	crtc->config.dpll_hw_state.dpll = dpll;





	I915_WRITE(DPLL(pipe), dpll);

	POSTING_READ(DPLL(pipe));

	udelay(150);



	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))

		DRM_ERROR("DPLL %d failed to lock\n", pipe);



	dpll_md = (crtc->config.pixel_multiplier - 1)

	dpll_md = (crtc->config.pixel_multiplier - 1)

		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;

		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;

	crtc->config.dpll_hw_state.dpll_md = dpll_md;

	crtc->config.dpll_hw_state.dpll_md = dpll_md;





	I915_WRITE(DPLL_MD(pipe), dpll_md);

	POSTING_READ(DPLL_MD(pipe));



	if (crtc->config.has_dp_encoder)

	if (crtc->config.has_dp_encoder)

		intel_dp_set_m_n(crtc);

		intel_dp_set_m_n(crtc);