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Commit 3a97f3ff authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Make couple functions in DCE80 TG static 



Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bbad2da8

drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c

+63 −62
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static const struct dce110_timing_generator_offsets reg_offsets[] = { 
#define DCP_REG(reg) (reg + tg110->offsets.dcp)

#define DMIF_REG(reg) (reg + tg110->offsets.dmif)



void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)

static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)

{

	uint64_t pix_dur;

	uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
@@ -115,6 +115,68 @@ static void program_timing(struct timing_generator *tg, 
	dce110_tg_program_timing(tg, timing, use_vbios);

}



static void dce80_timing_generator_enable_advanced_request(

	struct timing_generator *tg,

	bool enable,

	const struct dc_crtc_timing *timing)

{

	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);

	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);

	uint32_t value = dm_read_reg(tg->ctx, addr);



	if (enable) {

		set_reg_field_value(

			value,

			0,

			CRTC_START_LINE_CONTROL,

			CRTC_LEGACY_REQUESTOR_EN);

	} else {

		set_reg_field_value(

			value,

			1,

			CRTC_START_LINE_CONTROL,

			CRTC_LEGACY_REQUESTOR_EN);

	}



	if ((timing->v_sync_width + timing->v_front_porch) <= 3) {

		set_reg_field_value(

			value,

			3,

			CRTC_START_LINE_CONTROL,

			CRTC_ADVANCED_START_LINE_POSITION);

		set_reg_field_value(

			value,

			0,

			CRTC_START_LINE_CONTROL,

			CRTC_PREFETCH_EN);

	} else {

		set_reg_field_value(

			value,

			4,

			CRTC_START_LINE_CONTROL,

			CRTC_ADVANCED_START_LINE_POSITION);

		set_reg_field_value(

			value,

			1,

			CRTC_START_LINE_CONTROL,

			CRTC_PREFETCH_EN);

	}



	set_reg_field_value(

		value,

		1,

		CRTC_START_LINE_CONTROL,

		CRTC_PROGRESSIVE_START_LINE_EARLY);



	set_reg_field_value(

		value,

		1,

		CRTC_START_LINE_CONTROL,

		CRTC_INTERLACE_START_LINE_EARLY);



	dm_write_reg(tg->ctx, addr, value);

}



static const struct timing_generator_funcs dce80_tg_funcs = {

		.validate_timing = dce110_tg_validate_timing,

		.program_timing = program_timing,
@@ -176,64 +238,3 @@ void dce80_timing_generator_construct( 
	tg110->min_h_back_porch = 4;

}

void dce80_timing_generator_enable_advanced_request(

	struct timing_generator *tg,

	bool enable,

	const struct dc_crtc_timing *timing)

{

	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);

	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);

	uint32_t value = dm_read_reg(tg->ctx, addr);



	if (enable) {

		set_reg_field_value(

			value,

			0,

			CRTC_START_LINE_CONTROL,

			CRTC_LEGACY_REQUESTOR_EN);

	} else {

		set_reg_field_value(

			value,

			1,

			CRTC_START_LINE_CONTROL,

			CRTC_LEGACY_REQUESTOR_EN);

	}



	if ((timing->v_sync_width + timing->v_front_porch) <= 3) {

		set_reg_field_value(

			value,

			3,

			CRTC_START_LINE_CONTROL,

			CRTC_ADVANCED_START_LINE_POSITION);

		set_reg_field_value(

			value,

			0,

			CRTC_START_LINE_CONTROL,

			CRTC_PREFETCH_EN);

	} else {

		set_reg_field_value(

			value,

			4,

			CRTC_START_LINE_CONTROL,

			CRTC_ADVANCED_START_LINE_POSITION);

		set_reg_field_value(

			value,

			1,

			CRTC_START_LINE_CONTROL,

			CRTC_PREFETCH_EN);

	}



	set_reg_field_value(

		value,

		1,

		CRTC_START_LINE_CONTROL,

		CRTC_PROGRESSIVE_START_LINE_EARLY);



	set_reg_field_value(

		value,

		1,

		CRTC_START_LINE_CONTROL,

		CRTC_INTERLACE_START_LINE_EARLY);



	dm_write_reg(tg->ctx, addr, value);

}

drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h

+0 −6
Original line number Diff line number Diff line
@@ -36,10 +36,4 @@ void dce80_timing_generator_construct( 
	uint32_t instance,

	const struct dce110_timing_generator_offsets *offsets);



/******** HW programming ************/

void dce80_timing_generator_enable_advanced_request(

	struct timing_generator *tg,

	bool enable,

	const struct dc_crtc_timing *timing);



#endif /* __DC_TIMING_GENERATOR_DCE80_H__ */