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Commit 38b8f823 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
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clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset 



The register offset for the lcd1-ch1 clock was incorrectly pointing to
the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled
when the clk core disables unused clocks. This then stops the simplefb
HDMI output path.

Reported-by: default avatarBob Ham <rah@settrans.net>
Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Cc: stable@vger.kernel.org # 4.9.x-
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 2ea659a9

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -556,7 +556,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents, 
				 0x12c, 0, 4, 24, 3, BIT(31),

				 0x12c, 0, 4, 24, 3, BIT(31),

				 CLK_SET_RATE_PARENT);

				 CLK_SET_RATE_PARENT);

static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,

static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,

				 0x12c, 0, 4, 24, 3, BIT(31),

				 0x130, 0, 4, 24, 3, BIT(31),

				 CLK_SET_RATE_PARENT);

				 CLK_SET_RATE_PARENT);





static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",

static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",