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Commit c6e6c96d authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
Browse files

clk: sunxi-ng: Add A31/A31s clocks 



Add a new style driver for the clock control unit in Allwinner A31/A31s.

A few clocks are still missing:

    - MIPI PLL's HDMI mode support
    - EMAC clock

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 8adfb086

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ Allwinner Clock Control Unit Binding 
------------------------------------



Required properties :

- compatible: must contain one of the following compatible:

- compatible: must contain one of the following compatibles:

		- "allwinner,sun6i-a31-ccu"

		- "allwinner,sun8i-h3-ccu"



- reg: Must contain the registers base address and length

drivers/clk/sunxi-ng/Kconfig

+10 −0
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@@ -51,6 +51,16 @@ config SUNXI_CCU_MP 


# SoC Drivers



config SUN6I_A31_CCU

	bool "Support for the Allwinner A31/A31s CCU"

	select SUNXI_CCU_DIV

	select SUNXI_CCU_NK

	select SUNXI_CCU_NKM

	select SUNXI_CCU_NM

	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN6I



config SUN8I_H3_CCU

	bool "Support for the Allwinner H3 CCU"

	select SUNXI_CCU_DIV

drivers/clk/sunxi-ng/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -17,4 +17,5 @@ obj-$(CONFIG_SUNXI_CCU_NM) += ccu_nm.o 
obj-$(CONFIG_SUNXI_CCU_MP)	+= ccu_mp.o



# SoC support

obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o

obj-$(CONFIG_SUN8I_H3_CCU)	+= ccu-sun8i-h3.o

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

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+1235 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/sunxi-ng/ccu-sun6i-a31.h

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/*

 * Copyright 2016 Chen-Yu Tsai

 *

 * Chen-Yu Tsai <wens@csie.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _CCU_SUN6I_A31_H_

#define _CCU_SUN6I_A31_H_



#include <dt-bindings/clock/sun6i-a31-ccu.h>

#include <dt-bindings/reset/sun6i-a31-ccu.h>



#define CLK_PLL_CPU		0

#define CLK_PLL_AUDIO_BASE	1

#define CLK_PLL_AUDIO		2

#define CLK_PLL_AUDIO_2X	3

#define CLK_PLL_AUDIO_4X	4

#define CLK_PLL_AUDIO_8X	5

#define CLK_PLL_VIDEO0		6

#define CLK_PLL_VIDEO0_2X	7

#define CLK_PLL_VE		8

#define CLK_PLL_DDR		9



/* The PLL_PERIPH clock is exported */



#define CLK_PLL_PERIPH_2X	11

#define CLK_PLL_VIDEO1		12

#define CLK_PLL_VIDEO1_2X	13

#define CLK_PLL_GPU		14

#define CLK_PLL_MIPI		15

#define CLK_PLL9		16

#define CLK_PLL10		17



/* The CPUX clock is exported */



#define CLK_AXI			19

#define CLK_AHB1		20

#define CLK_APB1		21

#define CLK_APB2		22



/* All the bus gates are exported */



/* The first bunch of module clocks are exported */



/* EMAC clock is not implemented */



#define CLK_MDFS		107

#define CLK_SDRAM0		108

#define CLK_SDRAM1		109



/* All the DRAM gates are exported */



/* Some more module clocks are exported */



#define CLK_MBUS0		141

#define CLK_MBUS1		142



/* Some more module clocks and external clock outputs are exported */



#define CLK_NUMBER		(CLK_OUT_C + 1)



#endif /* _CCU_SUN6I_A31_H_ */