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Commit 3691feea authored by Alex Deucher's avatar Alex Deucher
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drm/radeon: check if pcie gen 2 is already enabled (v2)



If so, skip enabling it to save time.

v2: coding style fixes

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1a7ca0d
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+6 −1
Original line number Original line Diff line number Diff line
@@ -3431,9 +3431,14 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
	if (!(mask & DRM_PCIE_SPEED_50))
	if (!(mask & DRM_PCIE_SPEED_50))
		return;
		return;


	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
	if (speed_cntl & LC_CURRENT_DATA_RATE) {
		DRM_INFO("PCIE gen 2 link speeds already enabled\n");
		return;
	}

	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");


	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
	if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
	if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
	    (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
	    (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {


+6 −0
Original line number Original line Diff line number Diff line
@@ -3703,6 +3703,12 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
	if (!(mask & DRM_PCIE_SPEED_50))
	if (!(mask & DRM_PCIE_SPEED_50))
		return;
		return;


	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
	if (speed_cntl & LC_CURRENT_DATA_RATE) {
		DRM_INFO("PCIE gen 2 link speeds already enabled\n");
		return;
	}

	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");


	/* 55 nm r6xx asics */
	/* 55 nm r6xx asics */