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Commit 368483e3 authored by Sankeerth Billakanti's avatar Sankeerth Billakanti
Browse files

disp: msm: dp: use correct lane_count to validate mode 



The lane_count used for validating the display mode
to be set is wrongly taken from the initial panel
capability. So, when lane count is reduced during
link training, the reduced lane count will not be
considered for validating supported modes. Hence
reporting incorrect display modes.

This change will use the correct lane count which
is obtained after the link training sequence.

Change-Id: Iab6239280c29961f7bc6f945ff3ecee9954b0b73
Signed-off-by: default avatarSankeerth Billakanti <sbillaka@codeaurora.org>
parent 21372c65

msm/dp/dp_ctrl.c

+3 −2
Original line number Diff line number Diff line
@@ -996,14 +996,15 @@ static void dp_ctrl_mst_calculate_rg(struct dp_ctrl_private *ctrl, 
	u64 raw_target_sc, target_sc_fixp;

	u64 ts_denom, ts_enum, ts_int;

	u64 pclk = panel->pinfo.pixel_clk_khz;

	u64 lclk = panel->link_info.rate;

	u64 lanes = panel->link_info.num_lanes;

	u64 lclk = 0;

	u64 lanes = ctrl->link->link_params.lane_count;

	u64 bpp = panel->pinfo.bpp;

	u64 pbn = panel->pbn;

	u64 numerator, denominator, temp, temp1, temp2;

	u32 x_int = 0, y_frac_enum = 0;

	u64 target_strm_sym, ts_int_fixp, ts_frac_fixp, y_frac_enum_fixp;



	lclk = drm_dp_bw_code_to_link_rate(ctrl->link->link_params.bw_code);

	if (panel->pinfo.comp_info.comp_ratio)

		bpp = panel->pinfo.comp_info.dsc_info.bpp;

msm/dp/dp_display.c

+1 −4
Original line number Diff line number Diff line
@@ -2315,7 +2315,6 @@ static enum drm_mode_status dp_display_validate_mode( 
		const struct msm_resource_caps_info *avail_res)

{

	struct dp_display_private *dp;

	struct drm_dp_link *link_info;

	u32 mode_rate_khz = 0, supported_rate_khz = 0, mode_bpp = 0;

	struct dp_panel *dp_panel;

	struct dp_debug *debug;
@@ -2344,8 +2343,6 @@ static enum drm_mode_status dp_display_validate_mode( 
		goto end;

	}



	link_info = &dp->panel->link_info;



	debug = dp->debug;

	if (!debug)

		goto end;
@@ -2358,7 +2355,7 @@ static enum drm_mode_status dp_display_validate_mode( 


	mode_rate_khz = mode->clock * mode_bpp;

	rate = drm_dp_bw_code_to_link_rate(dp->link->link_params.bw_code);

	supported_rate_khz = link_info->num_lanes * rate * 8;

	supported_rate_khz = dp->link->link_params.lane_count * rate * 8;

	tmds_max_clock = dp_panel->connector->display_info.max_tmds_clock;



	if (mode_rate_khz > supported_rate_khz) {

msm/dp/dp_panel.c

+15 −6
Original line number Diff line number Diff line
@@ -1355,8 +1355,11 @@ static void _dp_panel_dsc_bw_overhead_calc(struct dp_panel *dp_panel, 
	int tot_num_hor_bytes, tot_num_dummy_bytes;

	int dwidth_dsc_bytes, eoc_bytes;

	u32 num_lanes;

	struct dp_panel_private *panel;



	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);



	num_lanes = dp_panel->link_info.num_lanes;

	num_lanes = panel->link->link_params.lane_count;

	num_slices = dsc->slice_per_pkt;



	eoc_bytes = dsc_byte_cnt % num_lanes;
@@ -2171,18 +2174,23 @@ static int dp_panel_read_sink_caps(struct dp_panel *dp_panel, 
static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel,

		u32 mode_edid_bpp, u32 mode_pclk_khz)

{

	struct drm_dp_link *link_info;

	struct dp_link_params *link_params;

	struct dp_panel_private *panel;

	const u32 max_supported_bpp = 30;

	u32 min_supported_bpp = 18;

	u32 bpp = 0, data_rate_khz = 0, tmds_max_clock = 0;



	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);



	if (dp_panel->dsc_en)

		min_supported_bpp = 24;



	bpp = min_t(u32, mode_edid_bpp, max_supported_bpp);



	link_info = &dp_panel->link_info;

	data_rate_khz = link_info->num_lanes * link_info->rate * 8;

	link_params = &panel->link->link_params;



	data_rate_khz = link_params->lane_count *

		drm_dp_bw_code_to_link_rate(link_params->bw_code) * 8;

	tmds_max_clock = dp_panel->connector->display_info.max_tmds_clock;



	for (; bpp > min_supported_bpp; bpp -= 6) {
@@ -2966,8 +2974,9 @@ static int dp_panel_setup_hdr(struct dp_panel *dp_panel, 
		dp_panel_setup_dhdr_vsif(panel);



		input.mdp_clk = core_clk_rate;

		input.lclk = dp_panel->link_info.rate;

		input.nlanes = dp_panel->link_info.num_lanes;

		input.lclk = drm_dp_bw_code_to_link_rate(

				panel->link->link_params.bw_code);

		input.nlanes = panel->link->link_params.lane_count;

		input.pclk = dp_panel->pinfo.pixel_clk_khz;

		input.h_active = dp_panel->pinfo.h_active;

		input.mst_target_sc = dp_panel->mst_target_sc;