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Commit 36075a4c authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Change BDW WIZ hashing mode to 16x4 



BSpec recommends using 8x4 hashing mode when MSAA is used. But in
practice 16x4 seems to have a slight edge in performance (on IVB and
HSW at least). So just use 16x4.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarAntti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a12c4967

drivers/gpu/drm/i915/intel_pm.c

+7 −0
Original line number Diff line number Diff line
@@ -4843,6 +4843,13 @@ static void gen8_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN7_FF_THREAD_MODE,

		   I915_READ(GEN7_FF_THREAD_MODE) &

		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));



	/*

	 * BSpec recommends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.

	 */

	I915_WRITE(GEN7_GT_MODE,

		   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);

}



static void haswell_init_clock_gating(struct drm_device *dev)