Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".

- #clock-cells : from common clock binding; Should always be set to 0.

- reg : Address and length of the axi-clkgen register set.

- clocks : Phandle and clock specifier for the parent clock.

- clocks : Phandle and clock specifier for the parent clock(s). This must

	either reference one clock if only the first clock input is connected or two

	if both clock inputs are connected. For the later case the clock connected

	to the first input must be specified first.

Optional properties:

- clock-output-names : From common clock binding.

    "brcm,cygnus-lcpll0"

    "brcm,cygnus-mipipll"

    "brcm,cygnus-asiu-clk"

    "brcm,cygnus-audiopll"

The following table defines the set of PLL/clock index and ID for Cygnus.

These clock IDs are defined in:

    ch4_unused mipipll          5       BCM_CYGNUS_MIPIPLL_CH4_UNUSED

    ch5_unused mipipll          6       BCM_CYGNUS_MIPIPLL_CH5_UNUSED

    audiopll   crystal          0       BCM_CYGNUS_AUDIOPLL

    ch0_audio  audiopll         1       BCM_CYGNUS_AUDIOPLL_CH0

    ch1_audio  audiopll         2       BCM_CYGNUS_AUDIOPLL_CH1

    ch2_audio  audiopll         3       BCM_CYGNUS_AUDIOPLL_CH2

Northstar and Northstar Plus

------

PLL and leaf clock compatible strings for Northstar and Northstar Plus are:

* NXP LPC1850 CREG clocks

The NXP LPC18xx/43xx CREG (Configuration Registers) block contains

control registers for two low speed clocks. One of the clocks is a

32 kHz oscillator driver with power up/down and clock gating. Next

is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.

These clocks are used by the RTC and the Event Router peripherials.

The 32 kHz can also be routed to other peripherials to enable low

power modes.

This binding uses the common clock binding:

    Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

- compatible:

	Should be "nxp,lpc1850-creg-clk"

- #clock-cells:

	Shall have value <1>.

- clocks:

	Shall contain a phandle to the fixed 32 kHz crystal.

The creg-clk node must be a child of the creg syscon node.

The following clocks are available from the clock node.

Clock ID	Name

   0		 1 kHz clock

   1		32 kHz Oscillator

Example:

soc {

	creg: syscon@40043000 {

		compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";

		reg = <0x40043000 0x1000>;

		creg_clk: clock-controller {

			compatible = "nxp,lpc1850-creg-clk";

			clocks = <&xtal32>;

			#clock-cells = <1>;

		};

		...

	};

	rtc: rtc@40046000 {

		...

		clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;

		clock-names = "rtc", "reg";

		...

	};

};

			"qcom,gcc-apq8064"

			"qcom,gcc-apq8084"

			"qcom,gcc-ipq8064"

			"qcom,gcc-ipq4019"

			"qcom,gcc-msm8660"

			"qcom,gcc-msm8916"

			"qcom,gcc-msm8960"

		reg = <0 0xe6e88000 0 64>;

		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cpg CPG_MOD 310>;

		clock-names = "sci_ick";

		clock-names = "fck";

		dmas = <&dmac1 0x13>, <&dmac1 0x12>;

		dma-names = "tx", "rx";

		power-domains = <&cpg>;