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Commit 3248a63a authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "drm/msm/dsi-staging: Update data lane control registers"

parents 51dd96e1 6895ae80

arch/arm64/boot/dts/qcom/kona-cdp.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -87,6 +87,15 @@ 
	qcom,platform-reset-gpio = <&tlmm 75 0>;

};



&dsi_sw43404_amoled_video {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <1023>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-reset-gpio = <&tlmm 75 0>;

};



&sde_dsi {

	qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;

};

arch/arm64/boot/dts/qcom/kona-mtp.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -312,6 +312,15 @@ 
	qcom,platform-reset-gpio = <&tlmm 75 0>;

};



&dsi_sw43404_amoled_video {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <1023>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-reset-gpio = <&tlmm 75 0>;

};



&sde_dsi {

	qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;

};

arch/arm64/boot/dts/qcom/kona-sde-display.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"

#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"

#include <dt-bindings/clock/mdss-7nm-pll-clk.h>



&soc {
@@ -101,3 +102,14 @@ 
		};

	};

};



&dsi_sw43404_amoled_video {

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05

				05 03 02 04 00 12 15];

			qcom,display-topology = <2 2 1>;

			qcom,default-topology-index = <0>;

		};

	};

};

drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c

+8 −1
Original line number Diff line number Diff line
@@ -113,7 +113,14 @@ static void dsi_phy_hw_v4_0_lane_settings(struct dsi_phy_hw *phy, 
			    struct dsi_phy_cfg *cfg)

{

	int i;

	u8 tx_dctrl[] = {0x00, 0x00, 0x00, 0x04, 0x01};

	u8 tx_dctrl_v4[] = {0x00, 0x00, 0x00, 0x04, 0x01};

	u8 tx_dctrl_v4_1[] = {0x40, 0x40, 0x40, 0x46, 0x41};

	u8 *tx_dctrl;



	if (phy->version == DSI_PHY_VERSION_4_1)

		tx_dctrl = &tx_dctrl_v4_1[0];

	else

		tx_dctrl = &tx_dctrl_v4[0];



	/* Strength ctrl settings */

	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {