Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 30346688 authored by Sunil Paidimarri's avatar Sunil Paidimarri Committed by Gerrit - the friendly Code Review server
Browse files

data-kernel: EMAC: Fix reset issue in ndo close 



Keep PHY RX clock enabled in LPI mode.
Update the MAC GMII speed as per link speed.

Change-Id: Ic312fc1c6e40a11ee041b3b997b222326e84ed71
CRs-Fixed: 2284587
Acked-by: default avatarRahul Kawadgave <rahulak@qti.qualcomm.com>
Signed-off-by: default avatarSunil Paidimarri <hisunil@codeaurora.org>
parent 39ea5418

drivers/emac-dwc-eqos/DWC_ETH_QOS_dev.c

+15 −1
Original line number Diff line number Diff line
@@ -4075,8 +4075,10 @@ static INT DWC_ETH_QOS_yexit(void) 
	/*Poll Until Poll Condition */

	vy_count = 0;

	while (1) {

		if (vy_count > RETRYCOUNT)

		if (vy_count > RETRYCOUNT) {

			EMACERR("Unable to reset MAC 0x%x\n", VARDMA_BMR);

			return -Y_FAILURE;

		}



		vy_count++;

		mdelay(1);
@@ -4691,6 +4693,18 @@ static INT configure_mac(struct DWC_ETH_QOS_prv_data *pdata) 
#endif

	MAC_MCR_RGWR(VARMAC_MCR);



	switch (pdata->speed) {

	case SPEED_1000:

		set_gmii_speed();

		break;

	case SPEED_100:

		set_mii_speed_100();

		break;

	case SPEED_10:

		set_mii_speed_10();

		break;

	}



	if (pdata->hw_feat.rx_coe_sel &&

	    ((pdata->dev_state & NETIF_F_RXCSUM) == NETIF_F_RXCSUM))

		MAC_MCR_IPC_UDFWR(0x1);

drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c

+22 −0
Original line number Diff line number Diff line
@@ -1947,6 +1947,7 @@ static int DWC_ETH_QOS_close(struct net_device *dev) 
	struct DWC_ETH_QOS_prv_data *pdata = netdev_priv(dev);

	struct hw_if_struct *hw_if = &pdata->hw_if;

	struct desc_if_struct *desc_if = &pdata->desc_if;

	int qinx = 0;



	DBGPR("-->DWC_ETH_QOS_close\n");
@@ -1959,7 +1960,15 @@ static int DWC_ETH_QOS_close(struct net_device *dev) 
		phy_stop(pdata->phydev);



#ifndef DWC_ETH_QOS_CONFIG_PGTEST

	/* Stop SW TX before DMA TX in HW */

	netif_tx_disable(dev);

	DWC_ETH_QOS_stop_all_ch_tx_dma(pdata);



	/* Disable MAC TX/RX */

	hw_if->stop_mac_tx_rx();



	/* Stop SW RX after DMA RX in HW */

	DWC_ETH_QOS_stop_all_ch_rx_dma(pdata);

	DWC_ETH_QOS_all_ch_napi_disable(pdata);



	if (pdata->ipa_enabled) {
@@ -1967,8 +1976,21 @@ static int DWC_ETH_QOS_close(struct net_device *dev) 
	}

#endif /* end of DWC_ETH_QOS_CONFIG_PGTEST */



#ifdef DWC_ETH_QOS_TXPOLLING_MODE_ENABLE

    for (qinx = 0; qinx < DWC_ETH_QOS_TX_QUEUE_CNT; qinx++) {

		/* check for tx descriptor status */

		DWC_ETH_QOS_tx_interrupt(pdata->dev, pdata, qinx);

    }

#endif



    for (qinx = 0; qinx < DWC_ETH_QOS_RX_QUEUE_CNT; qinx++)

        (void)pdata->clean_rx(pdata, NAPI_PER_QUEUE_POLL_BUDGET, qinx);



	/* issue software reset to device */

	hw_if->exit();



    DWC_ETH_QOS_restart_phy(pdata);



	desc_if->tx_free_mem(pdata);

	desc_if->rx_free_mem(pdata);

#ifdef PER_CH_INT

drivers/emac-dwc-eqos/DWC_ETH_QOS_eee.c

+4 −1
Original line number Diff line number Diff line
@@ -77,6 +77,9 @@ 
#define AR8035_SMART_EEE_CTRL_3 0x805D

#define AR8035_SMART_EEE_EN (1<<8)



#define PHY_RX_CLOCK_STOPPABLE_EN 1

#define PHY_RX_CLOCK_STOPPABLE_DIS 0



void DWC_ETH_QOS_enable_eee_mode(struct DWC_ETH_QOS_prv_data *pdata)

{

	struct DWC_ETH_QOS_tx_wrapper_descriptor *tx_desc_data = NULL;
@@ -426,7 +429,7 @@ bool DWC_ETH_QOS_eee_init(struct DWC_ETH_QOS_prv_data *pdata) 
#ifndef DWC_ETH_QOS_CUSTOMIZED_EEE_TEST

		/* check if the PHY supports EEE */

		if (!pdata->phydev || !pdata->phydev->link

			|| DWC_ETH_QOS_phy_init_eee(pdata->phydev, 1))

			|| DWC_ETH_QOS_phy_init_eee(pdata->phydev, PHY_RX_CLOCK_STOPPABLE_DIS))

			goto phy_eee_failed;

#endif /* DWC_ETH_QOS_CUSTOMIZED_EEE_TEST */

drivers/emac-dwc-eqos/DWC_ETH_QOS_platform.c

+2 −2
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ MODULE_PARM_DESC(phy_intf, "phy interface [rgmii, rmii, mii]"); 
static uint phy_intf_bypass_mode = INVALID_MODULE_PARAM_VAL;

module_param(phy_intf_bypass_mode, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);

MODULE_PARM_DESC(phy_intf_bypass_mode,

		 "Phy interface bypass mode [0-Non-ID, 1-ID]");

		 "Phy interface bypass mode [1-Non-ID, 0-ID]");



void DWC_ETH_QOS_init_all_fptrs(struct DWC_ETH_QOS_prv_data *pdata)

{
@@ -1207,7 +1207,7 @@ static int DWC_ETH_QOS_configure_netdevice(struct platform_device *pdev) 
			 continue;



		netif_napi_add(dev, &rx_queue->napi, DWC_ETH_QOS_poll_mq,

			  (64 * DWC_ETH_QOS_RX_QUEUE_CNT));

			  (NAPI_PER_QUEUE_POLL_BUDGET * DWC_ETH_QOS_RX_QUEUE_CNT));

	}



	dev->ethtool_ops = DWC_ETH_QOS_get_ethtool_ops();

drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h

+2 −0
Original line number Diff line number Diff line
@@ -654,6 +654,8 @@ 
#define MII_100_LOW_SVS_CLK_FREQ  (25 * 1000 * 1000UL)

#define MII_10_LOW_SVS_CLK_FREQ  (2.5 * 1000 * 1000UL)



#define NAPI_PER_QUEUE_POLL_BUDGET 64



/**

 * enum emac_hw_core_version - EMAC hardware core version type

* @EMAC_HW_None: EMAC hardware version not defined