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Commit 39ea5418 authored by Sunil Paidimarri's avatar Sunil Paidimarri Committed by Gerrit - the friendly Code Review server
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data-kernel: EMAC: Update IO Macro reset settings 



Update IO Macro reset settings for func clk.
Update reset function to support emac core version.
Update reset values for msmnile.

Change-Id: I82c556e1e0cdf57d74c2af0173899b6a2b41c8b9
CRS-Fixed: 2293623
Acked-by: default avatarRahul Kawadgave <rahulak@qti.qualcomm.com>
Signed-off-by: default avatarSunil Paidimarri <hisunil@codeaurora.org>
parent 9a4a3b61

drivers/emac-dwc-eqos/DWC_ETH_QOS_dev.c

+6 −2
Original line number Diff line number Diff line
@@ -4187,8 +4187,10 @@ static INT configure_tx_queue(UINT queue_index) 


	/*Poll Until Poll Condition */

	while (1) {

		if (vy_count > RETRYCOUNT)

		if (vy_count > RETRYCOUNT) {

			EMACERR("unable to flush tx queue %d", queue_index);

			return -Y_FAILURE;

		}

		vy_count++;

		usleep_range(1000, 1500);

		MTL_QTOMR_RGRD(queue_index, VARMTL_QTOMR);
@@ -4352,8 +4354,10 @@ static INT configure_mtl_queue(UINT QINX, struct DWC_ETH_QOS_prv_data *pdata) 
	/*Poll Until Poll Condition */

	vy_count = 0;

	while (1) {

		if (vy_count > RETRYCOUNT)

		if (vy_count > RETRYCOUNT){

			EMACERR("unable to flush tx queue %d", QINX);

			return -Y_FAILURE;

		}

		vy_count++;

		mdelay(1);

drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c

+3 −3
Original line number Diff line number Diff line
@@ -706,9 +706,9 @@ static inline int DWC_ETH_QOS_configure_io_macro_dll_settings( 
	EMACDBG("Enter\n");



	if (pdata->emac_hw_version_type == EMAC_HW_v2_0_0)

		DWC_ETH_QOS_rgmii_io_macro_dll_reset();



#ifndef DWC_ETH_QOS_EMULATION_PLATFORM

	DWC_ETH_QOS_rgmii_io_macro_dll_reset(pdata);



	/* For RGMII ID mode with internal delay*/

	if (pdata->io_macro_phy_intf == RGMII_MODE && !pdata->io_macro_tx_mode_non_id) {

		EMACDBG("Initialize and configure SDCC DLL\n");
@@ -1203,7 +1203,7 @@ int DWC_ETH_QOS_mdio_register(struct net_device *dev) 
	}

	if (pdata->io_macro_phy_intf == RMII_MODE) {

		pdata->speed = SPEED_100; //Default speed

		DWC_ETH_QOS_set_clk_and_bus_config(pdata);

		DWC_ETH_QOS_set_clk_and_bus_config(pdata, pdata->speed);

		ret = DWC_ETH_QOS_configure_io_macro_dll_settings(pdata);

		if (ret < 0) {

			EMACERR("Failed to configure IO macro and DLL settings\n");

drivers/emac-dwc-eqos/DWC_ETH_QOS_platform.c

+7 −0
Original line number Diff line number Diff line
@@ -1139,6 +1139,13 @@ static int DWC_ETH_QOS_configure_netdevice(struct platform_device *pdev) 


	/* store emac hw version in pdata*/

	pdata->emac_hw_version_type = dwc_eth_qos_res_data.emac_hw_version_type;



	/* Scale the clocks to 10Mbps speed */

	pdata->speed = SPEED_10;

	DWC_ETH_QOS_set_clk_and_bus_config(pdata, SPEED_10);



	DWC_ETH_QOS_set_rgmii_func_clk_en();



	/* issue software reset to device */

	hw_if->exit();

	/* IEMAC: Find and Read the IRQ from DTS */

drivers/emac-dwc-eqos/DWC_ETH_QOS_rgmii_io_macro.c

+124 −7
Original line number Diff line number Diff line
@@ -16,6 +16,95 @@ 
#include "DWC_ETH_QOS_yheader.h"

#include "DWC_ETH_QOS_yrgmii_io_macro_regacc.h"



/* RGMII IO MACRO power on reset values */

#define RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX 0

#define SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX 1

#define SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX 2

#define SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX 3

#define SDCC_USR_CTL_POR_ARR_INDEX 4

#define RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX 5



#define RGMII_IO_MACRO_DLL_POR_NUM_OF_REGS 6



#define RGMII_IO_MACRO_DLL_POR_REG_OFFSET_INDEX 0

#define RGMII_IO_MACRO_DLL_POR_REG_DATA_INDEX 1



ULONG rgmii_io_macro_dll_por_values

   [EMAC_HW_vMAX][RGMII_IO_MACRO_DLL_POR_NUM_OF_REGS][2] = {

	[EMAC_HW_None] = {

		[RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_RGOFFADDR_OFFSET, 0x0 },

		[SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_RGOFFADDR_OFFSET, 0x0 },

		[SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DDR_CONFIG_RGOFFADDR_OFFSET, 0x0 },

		[SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_2_RGOFFADDR_OFFSET, 0x0 },

		[SDCC_USR_CTL_POR_ARR_INDEX] = { SDCC_USR_CTL_RGOFFADDR_OFFSET, 0x0 },

		[RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_2_RGOFFADDR_OFFSET, 0x0 },

	},

	[EMAC_HW_v2_0_0] = {

		[RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_RGOFFADDR_OFFSET, 0x40C01343 },

		[SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_RGOFFADDR_OFFSET, 0x2004642C },

		[SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DDR_CONFIG_RGOFFADDR_OFFSET, 0x00000000 },

		[SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_2_RGOFFADDR_OFFSET, 0x00200000 },

		[SDCC_USR_CTL_POR_ARR_INDEX] = { SDCC_USR_CTL_RGOFFADDR_OFFSET, 0x00000000 },

		[RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_2_RGOFFADDR_OFFSET, 0x00002060 },

	},

	[EMAC_HW_v2_1_0] = {

		[RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_RGOFFADDR_OFFSET, 0x40C01343 },

		[SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_RGOFFADDR_OFFSET, 0x2004642C },

		[SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DDR_CONFIG_RGOFFADDR_OFFSET, 0x00000000 },

		[SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_2_RGOFFADDR_OFFSET, 0x00200000 },

		[SDCC_USR_CTL_POR_ARR_INDEX] = { SDCC_USR_CTL_RGOFFADDR_OFFSET, 0x00010800 },

		[RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_2_RGOFFADDR_OFFSET, 0x00002060 },

	},

	[EMAC_HW_v2_1_1] = {

		[RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_RGOFFADDR_OFFSET, 0x40C01343 },

		[SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_RGOFFADDR_OFFSET, 0x2004642C },

		[SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DDR_CONFIG_RGOFFADDR_OFFSET, 0x00000000 },

		[SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_2_RGOFFADDR_OFFSET, 0x00200000 },

		[SDCC_USR_CTL_POR_ARR_INDEX] = { SDCC_USR_CTL_RGOFFADDR_OFFSET, 0x00000000 },

		[RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_2_RGOFFADDR_OFFSET, 0x00002060 },

	},

	[EMAC_HW_v2_1_2] = {

		[RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_RGOFFADDR_OFFSET, 0x40C01343 },

		[SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_RGOFFADDR_OFFSET, 0x2004642C },

		[SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DDR_CONFIG_RGOFFADDR_OFFSET, 0x00000000 },

		[SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_2_RGOFFADDR_OFFSET, 0x00200000 },

		[SDCC_USR_CTL_POR_ARR_INDEX] = { SDCC_USR_CTL_RGOFFADDR_OFFSET, 0x00000000 },

		[RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_2_RGOFFADDR_OFFSET, 0x00002060 },

	},

	[EMAC_HW_v2_2_0] = {

		[RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_RGOFFADDR_OFFSET, 0x00C01343 },

		[SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_RGOFFADDR_OFFSET, 0x6004642C },

		[SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DDR_CONFIG_RGOFFADDR_OFFSET, 0x00000000 },

		[SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_2_RGOFFADDR_OFFSET, 0x00200000 },

		[SDCC_USR_CTL_POR_ARR_INDEX] = { SDCC_USR_CTL_RGOFFADDR_OFFSET, 0x00010800 },

		[RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_2_RGOFFADDR_OFFSET, 0x00002060 },

	},

	[EMAC_HW_v2_3_0] = {

		[RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_RGOFFADDR_OFFSET, 0x00C01343 },

		[SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_RGOFFADDR_OFFSET, 0x2004642C },

		[SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DDR_CONFIG_RGOFFADDR_OFFSET, 0x00000000 },

		[SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_2_RGOFFADDR_OFFSET, 0x00200000 },

		[SDCC_USR_CTL_POR_ARR_INDEX] = { SDCC_USR_CTL_RGOFFADDR_OFFSET, 0x00010800 },

		[RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_2_RGOFFADDR_OFFSET, 0x00002060 },

	},

	[EMAC_HW_v2_3_1] = {

		[RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_RGOFFADDR_OFFSET, 0x40C01343 },

		[SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_RGOFFADDR_OFFSET, 0x2004642C },

		[SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DDR_CONFIG_RGOFFADDR_OFFSET, 0x00000000 },

		[SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_2_RGOFFADDR_OFFSET, 0x00200000 },

		[SDCC_USR_CTL_POR_ARR_INDEX] = { SDCC_USR_CTL_RGOFFADDR_OFFSET, 0x00000000 },

		[RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_2_RGOFFADDR_OFFSET, 0x00002060 },

	},

	[EMAC_HW_v2_3_2] = {

		[RGMII_IO_MACRO_CONFIG_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_RGOFFADDR_OFFSET, 0x40C01343 },

		[SDCC_HC_REG_DLL_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_RGOFFADDR_OFFSET, 0x2004642C },

		[SDCC_HC_REG_DDR_CONFIG_POR_ARR_INDEX] = { SDCC_HC_REG_DDR_CONFIG_RGOFFADDR_OFFSET, 0x00000000 },

		[SDCC_HC_REG_DLL_CONFIG_2_POR_ARR_INDEX] = { SDCC_HC_REG_DLL_CONFIG_2_RGOFFADDR_OFFSET, 0x00200000 },

		[SDCC_USR_CTL_POR_ARR_INDEX] = { SDCC_USR_CTL_RGOFFADDR_OFFSET, 0x00000000 },

		[RGMII_IO_MACRO_CONFIG_2_POR_ARR_INDEX] = { RGMII_IO_MACRO_CONFIG_2_RGOFFADDR_OFFSET, 0x00002060 },

	},

};



/* SDCDC DLL initialization */

/*!

 * \brief Initialize the SDCDC
@@ -214,6 +303,23 @@ static int DWC_ETH_QOS_set_rgmii_loopback_mode(UINT lb_mode) 
	return Y_SUCCESS;

}



/* Programming rgmii_io_macro register for func_clk_en */

/*!

 * \brief Initialize the rgmii io macro block

 *

 * \details This function will write to the func_clk_en

 * fields in RGMII_IO_MACRO_CONFIG

 *

 *\return 0 on success

 */

int DWC_ETH_QOS_set_rgmii_func_clk_en(void)

{

	EMACDBG("Enter\n");

	RGMII_FUNC_CLK_EN_UDFWR(1);

	EMACDBG("Exit\n");

	return Y_SUCCESS;

}



/* Programming rgmii_io_macro register initialization */

/*!

 * \brief Initialize the rgmii io macro block
@@ -424,15 +530,26 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
 *

 *\return Y_SUCCESS

 */

int DWC_ETH_QOS_rgmii_io_macro_dll_reset(void)

int DWC_ETH_QOS_rgmii_io_macro_dll_reset(struct DWC_ETH_QOS_prv_data *pdata)

{

	int index_of_reg;

	ULONG data, address;

	EMACDBG("Enter\n");

	RGMII_IO_MACRO_CONFIG_RGWR(EMAC_RGMII_IO_MACRO_CONFIG_POR);

	RGMII_IO_MACRO_CONFIG_2_RGWR(EMAC_RGMII_IO_MACRO_CONFIG_2_POR);

	SDCC_HC_REG_DLL_CONFIG_RGWR(EMAC_SDCC_HC_REG_DLL_CONFIG_POR);

	SDCC_HC_REG_DDR_CONFIG_RGWR(EMAC_SDCC_HC_REG_DDR_CONFIG_POR);

	SDCC_HC_REG_DLL_CONFIG_2_RGWR(EMAC_SDCC_HC_REG_DLL_CONFIG_2_POR);

	SDCC_USR_CTL_RGWR(EMAC_SDCC_USR_CTL_POR);



	for (index_of_reg = 0 ; index_of_reg < RGMII_IO_MACRO_DLL_POR_NUM_OF_REGS; index_of_reg++) {

		address = RGMII_IO_BASE_ADDRESS

			+ rgmii_io_macro_dll_por_values

			[pdata->emac_hw_version_type]

			[index_of_reg]

			[RGMII_IO_MACRO_DLL_POR_REG_OFFSET_INDEX];

		data = rgmii_io_macro_dll_por_values

				[pdata->emac_hw_version_type]

				[index_of_reg]

				[RGMII_IO_MACRO_DLL_POR_REG_DATA_INDEX];

		iowrite32(data, (void *)address);

	}



	DWC_ETH_QOS_set_rgmii_func_clk_en();



	EMACDBG("Exit\n");

	return Y_SUCCESS;

drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h

+16 −22
Original line number Diff line number Diff line
@@ -666,17 +666,17 @@ 
* @EMAC_HW_v2_3_1: EMAC core version 2.3.1.

* @EMAC_HW_v2_3_2: EMAC core version 2.3.2.

*/

enum emac_core_version {

	EMAC_HW_None = 0,

	EMAC_HW_v2_0_0 = 1,

	EMAC_HW_v2_1_0 = 2,

	EMAC_HW_v2_1_1 = 3,

	EMAC_HW_v2_1_2 = 4,

	EMAC_HW_v2_2_0 = 5,

	EMAC_HW_v2_3_0 = 6,

	EMAC_HW_v2_3_1 = 7,

	EMAC_HW_v2_3_2 = 8

};



#define EMAC_HW_None 0

#define EMAC_HW_v2_0_0 1

#define EMAC_HW_v2_1_0 2

#define EMAC_HW_v2_1_1 3

#define EMAC_HW_v2_1_2 4

#define EMAC_HW_v2_2_0 5

#define EMAC_HW_v2_3_0 6

#define EMAC_HW_v2_3_1 7

#define EMAC_HW_v2_3_2 8

#define EMAC_HW_vMAX 9





/* C data types typedefs */
@@ -1523,7 +1523,7 @@ struct DWC_ETH_QOS_res_data { 
	struct clk *ahb_clk;

	struct clk *rgmii_clk;

	struct clk *ptp_clk;

	enum emac_core_version emac_hw_version_type;

	unsigned int emac_hw_version_type;

};



struct DWC_ETH_QOS_prv_ipa_data {
@@ -1775,7 +1775,7 @@ struct DWC_ETH_QOS_prv_data { 
	unsigned int io_macro_tx_mode_non_id;

	unsigned int io_macro_phy_intf;

	int phy_irq;

	enum emac_core_version emac_hw_version_type;

	unsigned int emac_hw_version_type;



	/* Work struct for handling phy interrupt */

	struct work_struct emac_phy_work;
@@ -1905,16 +1905,10 @@ int DWC_ETH_QOS_rgmii_io_macro_sdcdc_enable_lp_mode(void); 
int DWC_ETH_QOS_rgmii_io_macro_sdcdc_config(void);

int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *);

int DWC_ETH_QOS_sdcc_set_bypass_mode(void);

int DWC_ETH_QOS_rgmii_io_macro_dll_reset(void);

int DWC_ETH_QOS_rgmii_io_macro_dll_reset(struct DWC_ETH_QOS_prv_data *pdata);

void dump_rgmii_io_macro_registers(void);



/* POR values for IO macro and DLL registers */

#define EMAC_RGMII_IO_MACRO_CONFIG_POR 0x40C01343

#define EMAC_RGMII_IO_MACRO_CONFIG_2_POR 0x00002060

#define EMAC_SDCC_HC_REG_DLL_CONFIG_POR 0x2004642C

#define EMAC_SDCC_HC_REG_DDR_CONFIG_POR 0x00000000

#define EMAC_SDCC_HC_REG_DLL_CONFIG_2_POR 0x00200000

#define EMAC_SDCC_USR_CTL_POR 0x00000000

int DWC_ETH_QOS_set_rgmii_func_clk_en(void);

void DWC_ETH_QOS_set_clk_and_bus_config(struct DWC_ETH_QOS_prv_data *pdata, int speed);



#define EMAC_MDC "dev-emac-mdc"

#define EMAC_MDIO "dev-emac-mdio"