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Commit 30076117 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: update clock_rpmh device node for KONA"

parents 10e27a32 ee6a9d64

Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt

+10 −1
Original line number Diff line number Diff line
@@ -6,7 +6,9 @@ some Qualcomm Technologies Inc. SoCs. It accepts clock requests from 
other hardware subsystems via RSC to control clocks.



Required properties :

- compatible : shall contain "qcom,sdm845-rpmh-clk"

- compatible : Shall contain one of the following:

		"qcom,kona-rpmh-clk",

		"qcom,sdm845-rpmh-clk"



- #clock-cells : must contain 1
@@ -20,3 +22,10 @@ Example : 
			#clock-cells = <1>;

		};

	};



	&apps_rsc {

		rpmhcc: clock-controller {

			compatible = "qcom,kona-rpmh-clk";

			#clock-cells = <1>;

		};

	};

arch/arm64/boot/dts/qcom/kona.dtsi

+14 −15
Original line number Diff line number Diff line
@@ -399,7 +399,7 @@ 
			reg-names = "freq-domain0", "freq-domain1",

				"freq-domain2";



			clocks = <&clock_xo>, <&clock_gcc GPLL0>;

			clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GPLL0>;

			clock-names = "xo", "cpu_clk";



			#freq-domain-cells = <2>;
@@ -881,14 +881,14 @@ 
		interrupt-controller;

	};



	clock_xo: bi_tcxo {

	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			#clock-cells = <0>;

		clock-frequency = <19200000>;

		clock-output-names = "bi_tcxo";

			clock-frequency = <38400000>;

			clock-output-names = "xo_board";

		};



	clocks {

		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32000>;
@@ -897,12 +897,6 @@ 
		};

	};



	clock_rpmh: qcom,rpmhclk {

		compatible = "qcom,dummycc";

		clock-output-names = "rpmh_clocks";

		#clock-cells = <1>;

	};



	clock_aop: qcom,aopclk {

		compatible = "qcom,dummycc";

		clock-output-names = "qdss_clocks";
@@ -986,7 +980,7 @@ 
		qcom,camcc = <&clock_camcc>;

		qcom,gpucc = <&clock_gpucc>;

		clock-names = "xo_clk_src";

		clocks = <&clock_xo>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		#clock-cells = <1>;

	};
@@ -1418,6 +1412,11 @@ 
		system_pm {

			compatible = "qcom,system-pm";

		};



		clock_rpmh: qcom,rpmhclk {

			compatible = "qcom,kona-rpmh-clk";

			#clock-cells = <1>;

		};

	};



	disp_rsc: rsc@af20000 {

arch/arm64/configs/vendor/kona-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -411,6 +411,7 @@ CONFIG_RNDIS_IPA=y 
CONFIG_MSM_11AD=m

CONFIG_USB_BAM=y

CONFIG_QCOM_GENI_SE=y

CONFIG_QCOM_CLK_RPMH=y

CONFIG_SPMI_PMIC_CLKDIV=y

CONFIG_MSM_GCC_KONA=y

CONFIG_MSM_VIDEOCC_KONA=y

arch/arm64/configs/vendor/kona_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -425,6 +425,7 @@ CONFIG_RNDIS_IPA=y 
CONFIG_MSM_11AD=m

CONFIG_USB_BAM=y

CONFIG_QCOM_GENI_SE=y

CONFIG_QCOM_CLK_RPMH=y

CONFIG_SPMI_PMIC_CLKDIV=y

CONFIG_MSM_GCC_KONA=y

CONFIG_MSM_VIDEOCC_KONA=y

drivers/clk/qcom/clk-rpmh.c

+61 −4
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/clk-provider.h>
@@ -36,6 +36,7 @@ struct clk_rpmh { 
	struct clk_hw hw;

	const char *res_name;

	u8 div;

	bool optional;

	u32 res_addr;

	u32 res_on_val;

	u32 state;
@@ -54,13 +55,14 @@ struct clk_rpmh_desc { 
static DEFINE_MUTEX(rpmh_clk_lock);



#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  _res_en_offset, _res_on, _div)		\

			  _res_en_offset, _res_on, _div, _optional)	\

	static struct clk_rpmh _platform##_##_name_active;		\

	static struct clk_rpmh _platform##_##_name = {			\

		.res_name = _res_name,					\

		.res_addr = _res_en_offset,				\

		.res_on_val = _res_on,					\

		.div = _div,						\

		.optional = _optional,					\

		.peer = &_platform##_##_name_active,			\

		.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |	\

				      BIT(RPMH_ACTIVE_ONLY_STATE) |	\
@@ -77,6 +79,7 @@ static DEFINE_MUTEX(rpmh_clk_lock); 
		.res_addr = _res_en_offset,				\

		.res_on_val = _res_on,					\

		.div = _div,						\

		.optional = _optional,					\

		.peer = &_platform##_##_name,				\

		.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |	\

					BIT(RPMH_ACTIVE_ONLY_STATE)),	\
@@ -91,12 +94,19 @@ static DEFINE_MUTEX(rpmh_clk_lock); 
#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name,	\

			    _res_on, _div)				\

	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)

			  CLK_RPMH_ARC_EN_OFFSET, _res_on, _div, false)



#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name,	\

				_div)					\

	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  CLK_RPMH_VRM_EN_OFFSET, 1, _div)

			  CLK_RPMH_VRM_EN_OFFSET, 1, _div, false)



#define DEFINE_CLK_RPMH_VRM_OPT(_platform, _name, _name_active,		\

			_res_name, _div)				\

	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  CLK_RPMH_VRM_EN_OFFSET, 1, _div, true)







static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)

{
@@ -238,17 +248,58 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = { 
	.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),

};



DEFINE_CLK_RPMH_ARC(kona, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);

DEFINE_CLK_RPMH_VRM(kona, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);

DEFINE_CLK_RPMH_VRM(kona, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);

DEFINE_CLK_RPMH_VRM(kona, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);

DEFINE_CLK_RPMH_VRM(kona, rf_clk1, rf_clk1_ao, "rfclka1", 1);

DEFINE_CLK_RPMH_VRM(kona, rf_clk3, rf_clk3_ao, "rfclka3", 1);

DEFINE_CLK_RPMH_VRM_OPT(kona, rf_clkd3, rf_clkd3_ao, "rfclkd3", 1);

DEFINE_CLK_RPMH_VRM_OPT(kona, rf_clkd4, rf_clkd4_ao, "rfclkd4", 1);



static struct clk_hw *kona_rpmh_clocks[] = {

	[RPMH_CXO_CLK]		= &kona_bi_tcxo.hw,

	[RPMH_CXO_CLK_A]	= &kona_bi_tcxo_ao.hw,

	[RPMH_LN_BB_CLK1]	= &kona_ln_bb_clk1.hw,

	[RPMH_LN_BB_CLK1_A]	= &kona_ln_bb_clk1_ao.hw,

	[RPMH_LN_BB_CLK2]	= &kona_ln_bb_clk2.hw,

	[RPMH_LN_BB_CLK2_A]	= &kona_ln_bb_clk2_ao.hw,

	[RPMH_LN_BB_CLK3]	= &kona_ln_bb_clk3.hw,

	[RPMH_LN_BB_CLK3_A]	= &kona_ln_bb_clk3_ao.hw,

	[RPMH_RF_CLK1]		= &kona_rf_clk1.hw,

	[RPMH_RF_CLK1_A]	= &kona_rf_clk1_ao.hw,

	[RPMH_RF_CLK3]		= &kona_rf_clk3.hw,

	[RPMH_RF_CLK3_A]	= &kona_rf_clk3_ao.hw,

	[RPMH_RF_CLKD3]		= &kona_rf_clkd3.hw,

	[RPMH_RF_CLKD3_A]	= &kona_rf_clkd3_ao.hw,

	[RPMH_RF_CLKD4]		= &kona_rf_clkd4.hw,

	[RPMH_RF_CLKD4_A]	= &kona_rf_clkd4_ao.hw,

};



static const struct clk_rpmh_desc clk_rpmh_kona = {

	.clks = kona_rpmh_clocks,

	.num_clks = ARRAY_SIZE(kona_rpmh_clocks),

};



static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,

					 void *data)

{

	struct clk_rpmh_desc *rpmh = data;

	unsigned int idx = clkspec->args[0];

	struct clk_rpmh *c;



	if (idx >= rpmh->num_clks) {

		pr_err("%s: invalid index %u\n", __func__, idx);

		return ERR_PTR(-EINVAL);

	}



	if (!rpmh->clks[idx])

		return ERR_PTR(-ENOENT);



	c = to_clk_rpmh(rpmh->clks[idx]);

	if (!c->res_addr)

		return ERR_PTR(-ENODEV);



	return rpmh->clks[idx];

}
@@ -268,9 +319,14 @@ static int clk_rpmh_probe(struct platform_device *pdev) 
	for (i = 0; i < desc->num_clks; i++) {

		u32 res_addr;



		if (!hw_clks[i])

			continue;



		rpmh_clk = to_clk_rpmh(hw_clks[i]);

		res_addr = cmd_db_read_addr(rpmh_clk->res_name);

		if (!res_addr) {

			if (rpmh_clk->optional)

				continue;

			dev_err(&pdev->dev, "missing RPMh resource address for %s\n",

				rpmh_clk->res_name);

			return -ENODEV;
@@ -301,6 +357,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) 


static const struct of_device_id clk_rpmh_match_table[] = {

	{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},

	{ .compatible = "qcom,kona-rpmh-clk", .data = &clk_rpmh_kona},

	{ }

};

MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);