Loading msm/dsi/dsi_ctrl_hw_cmn.c +8 −0 Original line number Diff line number Diff line Loading @@ -92,6 +92,14 @@ void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl, dsi_setup_trigger_controls(ctrl, cfg); dsi_split_link_setup(ctrl, cfg); /* Setup T_CLK_PRE extend register */ reg_value = DSI_R32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_ENABLE); if (cfg->t_clk_pre_extend) reg_value |= BIT(0); else reg_value &= ~BIT(0); DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_ENABLE, reg_value); /* Setup clocking timing controls */ reg_value = ((cfg->t_clk_post & 0x3F) << 8); reg_value |= (cfg->t_clk_pre & 0x3F); Loading msm/dsi/dsi_defs.h +3 −0 Original line number Diff line number Diff line Loading @@ -479,6 +479,8 @@ struct dsi_split_link_config { * @t_clk_pre: Number of byte clock cycles that the high spped clock * shall be driven prior to data lane transitions from LP * to HS mode. * @t_clk_pre_extend: Increment t_clk_pre counter by 2 byteclk if set to * true, otherwise increment by 1 byteclk. * @ignore_rx_eot: Ignore Rx EOT packets if set to true. * @append_tx_eot: Append EOT packets for forward transmissions if set to * true. Loading @@ -505,6 +507,7 @@ struct dsi_host_common_cfg { bool bit_swap_blue; u32 t_clk_post; u32 t_clk_pre; bool t_clk_pre_extend; bool ignore_rx_eot; bool append_tx_eot; bool ext_bridge_mode; Loading msm/dsi/dsi_panel.c +3 −0 Original line number Diff line number Diff line Loading @@ -1198,6 +1198,9 @@ static int dsi_panel_parse_misc_host_config(struct dsi_host_common_cfg *host, DSI_DEBUG("[%s] t_clk_pre = %d\n", name, val); } host->t_clk_pre_extend = utils->read_bool(utils->data, "qcom,mdss-dsi-t-clk-pre-extend"); host->ignore_rx_eot = utils->read_bool(utils->data, "qcom,mdss-dsi-rx-eot-ignore"); Loading Loading
msm/dsi/dsi_ctrl_hw_cmn.c +8 −0 Original line number Diff line number Diff line Loading @@ -92,6 +92,14 @@ void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl, dsi_setup_trigger_controls(ctrl, cfg); dsi_split_link_setup(ctrl, cfg); /* Setup T_CLK_PRE extend register */ reg_value = DSI_R32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_ENABLE); if (cfg->t_clk_pre_extend) reg_value |= BIT(0); else reg_value &= ~BIT(0); DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_ENABLE, reg_value); /* Setup clocking timing controls */ reg_value = ((cfg->t_clk_post & 0x3F) << 8); reg_value |= (cfg->t_clk_pre & 0x3F); Loading
msm/dsi/dsi_defs.h +3 −0 Original line number Diff line number Diff line Loading @@ -479,6 +479,8 @@ struct dsi_split_link_config { * @t_clk_pre: Number of byte clock cycles that the high spped clock * shall be driven prior to data lane transitions from LP * to HS mode. * @t_clk_pre_extend: Increment t_clk_pre counter by 2 byteclk if set to * true, otherwise increment by 1 byteclk. * @ignore_rx_eot: Ignore Rx EOT packets if set to true. * @append_tx_eot: Append EOT packets for forward transmissions if set to * true. Loading @@ -505,6 +507,7 @@ struct dsi_host_common_cfg { bool bit_swap_blue; u32 t_clk_post; u32 t_clk_pre; bool t_clk_pre_extend; bool ignore_rx_eot; bool append_tx_eot; bool ext_bridge_mode; Loading
msm/dsi/dsi_panel.c +3 −0 Original line number Diff line number Diff line Loading @@ -1198,6 +1198,9 @@ static int dsi_panel_parse_misc_host_config(struct dsi_host_common_cfg *host, DSI_DEBUG("[%s] t_clk_pre = %d\n", name, val); } host->t_clk_pre_extend = utils->read_bool(utils->data, "qcom,mdss-dsi-t-clk-pre-extend"); host->ignore_rx_eot = utils->read_bool(utils->data, "qcom,mdss-dsi-rx-eot-ignore"); Loading