Commit 228df561 authored Feb 18, 2020 by Lipsa Rout Committed by Ritesh Kumar Mar 13, 2020

techpack: disp: pll: Fix the clk get rate check in dsi pll



Updates the clk get rate check in dsi pll. This fixes
display clock voting for SVS instead of LSVS issue.

Change-Id: Ibdedd8f476d7a38858d18d233517699b61cf76f1
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>

parent 42a3ef70

pll/dsi_pll_10nm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1161,7 +1161,7 @@ static int vco_10nm_prepare(struct clk_hw *hw)
		}

		if ((pll->vco_cached_rate != 0) &&
		(pll->vco_cached_rate == clk_get_rate(hw->clk))) {
		(pll->vco_cached_rate == clk_hw_get_rate(hw))) {
		rc = hw->init->ops->set_rate(hw, pll->vco_cached_rate,
		pll->vco_cached_rate);
		if (rc) {