Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1d40cfcd authored by Ralf Baechle's avatar Ralf Baechle
Browse files

Avoid SMP cacheflushes. This is a minor optimization of startup but 


will also avoid smp_call_function from doing stupid things when called
from a CPU that is not yet marked online.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent bdf21b18

arch/mips/kernel/traps.c

+2 −0
Original line number Diff line number Diff line
@@ -1150,6 +1150,7 @@ static inline void signal32_init(void) 


extern void cpu_cache_init(void);

extern void tlb_init(void);

extern void flush_tlb_handlers(void);



void __init per_cpu_trap_init(void)

{
@@ -1348,4 +1349,5 @@ void __init trap_init(void) 
#endif



	flush_icache_range(ebase, ebase + 0x400);

	flush_tlb_handlers();

}

arch/mips/mm/c-r4k.c

+2 −3
Original line number Diff line number Diff line
@@ -1270,9 +1270,8 @@ void __init ld_mmu_r4xx0(void) 
	_dma_cache_inv		= r4k_dma_cache_inv;

#endif



	__flush_cache_all();

	coherency_setup();



	build_clear_page();

	build_copy_page();

	local_r4k___flush_cache_all(NULL);

	coherency_setup();

}

arch/mips/mm/c-tx39.c

+1 −0
Original line number Diff line number Diff line
@@ -492,4 +492,5 @@ void __init ld_mmu_tx39(void) 


	build_clear_page();

	build_copy_page();

	tx39h_flush_icache_all();

}

arch/mips/mm/pg-r4k.c

+0 −6
Original line number Diff line number Diff line
@@ -404,9 +404,6 @@ dest = label(); 


	build_jr_ra();



	flush_icache_range((unsigned long)&clear_page_array,

	                   (unsigned long) epc);



	BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));

}
@@ -482,8 +479,5 @@ dest = label(); 


	build_jr_ra();



	flush_icache_range((unsigned long)&copy_page_array,

	                   (unsigned long) epc);



	BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));

}

arch/mips/mm/tlbex.c

+10 −20
Original line number Diff line number Diff line
@@ -743,7 +743,6 @@ static void __init build_r3000_tlb_refill_handler(void) 
#endif



	memcpy((void *)CAC_BASE, tlb_handler, 0x80);

	flush_icache_range(CAC_BASE, CAC_BASE + 0x80);

}



/*
@@ -1258,7 +1257,6 @@ static void __init build_r4000_tlb_refill_handler(void) 
#endif



	memcpy((void *)CAC_BASE, final_handler, 0x100);

	flush_icache_range(CAC_BASE, CAC_BASE + 0x100);

}



/*
@@ -1519,9 +1517,6 @@ static void __init build_r3000_tlb_load_handler(void) 
			printk("%08x\n", handle_tlbl[i]);

	}

#endif



	flush_icache_range((unsigned long)handle_tlbl,

			   (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));

}



static void __init build_r3000_tlb_store_handler(void)
@@ -1559,9 +1554,6 @@ static void __init build_r3000_tlb_store_handler(void) 
			printk("%08x\n", handle_tlbs[i]);

	}

#endif



	flush_icache_range((unsigned long)handle_tlbs,

			   (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));

}



static void __init build_r3000_tlb_modify_handler(void)
@@ -1599,9 +1591,6 @@ static void __init build_r3000_tlb_modify_handler(void) 
			printk("%08x\n", handle_tlbm[i]);

	}

#endif



	flush_icache_range((unsigned long)handle_tlbm,

			   (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));

}



/*
@@ -1691,9 +1680,6 @@ static void __init build_r4000_tlb_load_handler(void) 
			printk("%08x\n", handle_tlbl[i]);

	}

#endif



	flush_icache_range((unsigned long)handle_tlbl,

			   (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));

}



static void __init build_r4000_tlb_store_handler(void)
@@ -1730,9 +1716,6 @@ static void __init build_r4000_tlb_store_handler(void) 
			printk("%08x\n", handle_tlbs[i]);

	}

#endif



	flush_icache_range((unsigned long)handle_tlbs,

			   (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));

}



static void __init build_r4000_tlb_modify_handler(void)
@@ -1770,9 +1753,6 @@ static void __init build_r4000_tlb_modify_handler(void) 
			printk("%08x\n", handle_tlbm[i]);

	}

#endif



	flush_icache_range((unsigned long)handle_tlbm,

			   (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));

}



void __init build_tlb_refill_handler(void)
@@ -1820,3 +1800,13 @@ void __init build_tlb_refill_handler(void) 
		}

	}

}



void __init flush_tlb_handlers(void)

{

	flush_icache_range((unsigned long)handle_tlbl,

			   (unsigned long)handle_tlbl + sizeof(handle_tlbl));

	flush_icache_range((unsigned long)handle_tlbs,

			   (unsigned long)handle_tlbs + sizeof(handle_tlbs));

	flush_icache_range((unsigned long)handle_tlbm,

			   (unsigned long)handle_tlbm + sizeof(handle_tlbm));

}