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Commit 18ec0e70 authored by Kevin Cernekee's avatar Kevin Cernekee Committed by John Crispin
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MIPS: BCM63XX: Add register definitions for USBD dependencies 



The USB 2.0 device depends on some functionality in other blocks, such
as GPIO and USBH.  Add those register definitions here.

Signed-off-by: default avatarKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4025/


Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
parent 6f942345

arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h

+3 −3
Original line number Diff line number Diff line
@@ -184,9 +184,9 @@ enum bcm63xx_regs_set { 
#define BCM_6328_SPI_BASE		(0xdeadbeef)

#define BCM_6328_UDC0_BASE		(0xdeadbeef)

#define BCM_6328_USBDMA_BASE		(0xdeadbeef)

#define BCM_6328_OHCI0_BASE		(0xdeadbeef)

#define BCM_6328_OHCI0_BASE		(0xb0002600)

#define BCM_6328_OHCI_PRIV_BASE		(0xdeadbeef)

#define BCM_6328_USBH_PRIV_BASE		(0xdeadbeef)

#define BCM_6328_USBH_PRIV_BASE		(0xb0002700)

#define BCM_6328_MPI_BASE		(0xdeadbeef)

#define BCM_6328_PCMCIA_BASE		(0xdeadbeef)

#define BCM_6328_PCIE_BASE		(0xb0e40000)
@@ -199,7 +199,7 @@ enum bcm63xx_regs_set { 
#define BCM_6328_ENETDMAC_BASE		(0xb000da00)

#define BCM_6328_ENETDMAS_BASE		(0xb000dc00)

#define BCM_6328_ENETSW_BASE		(0xb0e00000)

#define BCM_6328_EHCI0_BASE		(0x10002500)

#define BCM_6328_EHCI0_BASE		(0xb0002500)

#define BCM_6328_SDRAM_BASE		(0xdeadbeef)

#define BCM_6328_MEMC_BASE		(0xdeadbeef)

#define BCM_6328_DDR_BASE		(0xb0003000)

arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h

+8 −0
Original line number Diff line number Diff line
@@ -543,6 +543,12 @@ 
#define GPIO_MODE_6368_SPI_SSN5		(1 << 31)





#define GPIO_PINMUX_OTHR_REG		0x24

#define GPIO_PINMUX_OTHR_6328_USB_SHIFT	12

#define GPIO_PINMUX_OTHR_6328_USB_MASK	(3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)

#define GPIO_PINMUX_OTHR_6328_USB_HOST	(1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)

#define GPIO_PINMUX_OTHR_6328_USB_DEV	(2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)



#define GPIO_BASEMODE_6368_REG		0x38

#define GPIO_BASEMODE_6368_UART2	0x1

#define GPIO_BASEMODE_6368_GPIO		0x0
@@ -778,6 +784,8 @@ 
#define USBH_PRIV_SWAP_6358_REG		0x0

#define USBH_PRIV_SWAP_6368_REG		0x1c



#define USBH_PRIV_SWAP_USBD_SHIFT	6

#define USBH_PRIV_SWAP_USBD_MASK	(1 << USBH_PRIV_SWAP_USBD_SHIFT)

#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT	4

#define USBH_PRIV_SWAP_EHCI_ENDN_MASK	(1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)

#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT	3