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Commit 18dc37df authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add the phandle of crypto core for PIL's on Bengal"

parents 5e4788b9 50ac34ac
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+2 −0
Original line number Diff line number Diff line
@@ -91,6 +91,8 @@ Optional properties:

- qcom,minidump-as-elf32: Boolean. If set, minidump is collected in ELF32 format.

- qcom,mas-crypto: phandle to the bus master of crypto core.

Example:
	qcom,venus@fdce0000 {
		compatible = "qcom,pil-tz-generic";
+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@
		compatible = "qcom,pil-tz-generic";
		qcom,pas-id = <13>;
		qcom,firmware-name = "a610_zap";
		qcom,mas-crypto = <&mas_crypto_c0>;
	};

	gpu_opp_table: gpu-opp-table {
+4 −0
Original line number Diff line number Diff line
@@ -1008,6 +1008,7 @@
		clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		qcom,mas-crypto = <&mas_crypto_c0>;

		qcom,pas-id = <1>;
		qcom,proxy-timeout-ms = <10000>;
@@ -1047,6 +1048,7 @@
		clocks = <&rpmcc CXO_SMD_PIL_CDSP_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		qcom,mas-crypto = <&mas_crypto_c0>;

		qcom,pas-id = <18>;
		qcom,proxy-timeout-ms = <10000>;
@@ -2129,6 +2131,7 @@
			<&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
		clock-names = "xo_clock", "core_clk", "bus_clk", "iface_clk", "video_bus0_clk", "video_iface_clk", "throttle_clk";
		qcom,proxy-clock-names = "xo_clock", "core_clk", "bus_clk", "iface_clk", "video_bus0_clk", "video_iface_clk", "throttle_clk";
		qcom,mas-crypto = <&mas_crypto_c0>;

		qcom,core-freq = <240000000>;
		qcom,ahb-freq = <240000000>;
@@ -2152,6 +2155,7 @@
		clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		qcom,mas-crypto = <&mas_crypto_c0>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;