Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 50ac34ac authored by Shadab Naseem's avatar Shadab Naseem
Browse files

ARM: dts: msm: Add the phandle of crypto core for PIL's on Bengal 

Add the phandle entry of bus master crypto core for PIL's like
(lpass, turing, mss, venus, gpu) for Bengal.
Also update Documentation for mas-crypto entry.

Change-Id: I535d523cd96bd82764e8b1875c31b52523f625c4
parent f701f554

bindings/pil/subsys-pil-tz.txt

+2 −0
Original line number Diff line number Diff line
@@ -91,6 +91,8 @@ Optional properties: 


- qcom,minidump-as-elf32: Boolean. If set, minidump is collected in ELF32 format.



- qcom,mas-crypto: phandle to the bus master of crypto core.



Example:

	qcom,venus@fdce0000 {

		compatible = "qcom,pil-tz-generic";

qcom/bengal-gpu.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
		compatible = "qcom,pil-tz-generic";

		qcom,pas-id = <13>;

		qcom,firmware-name = "a610_zap";

		qcom,mas-crypto = <&mas_crypto_c0>;

	};



	gpu_opp_table: gpu-opp-table {

qcom/bengal.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -744,6 +744,7 @@ 
		clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>;

		clock-names = "xo";

		qcom,proxy-clock-names = "xo";

		qcom,mas-crypto = <&mas_crypto_c0>;



		qcom,pas-id = <1>;

		qcom,proxy-timeout-ms = <10000>;
@@ -783,6 +784,7 @@ 
		clocks = <&rpmcc CXO_SMD_PIL_CDSP_CLK>;

		clock-names = "xo";

		qcom,proxy-clock-names = "xo";

		qcom,mas-crypto = <&mas_crypto_c0>;



		qcom,pas-id = <18>;

		qcom,proxy-timeout-ms = <10000>;
@@ -1589,6 +1591,7 @@ 
			<&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;

		clock-names = "xo_clock", "core_clk", "bus_clk", "iface_clk", "video_bus0_clk", "video_iface_clk", "throttle_clk";

		qcom,proxy-clock-names = "xo_clock", "core_clk", "bus_clk", "iface_clk", "video_bus0_clk", "video_iface_clk", "throttle_clk";

		qcom,mas-crypto = <&mas_crypto_c0>;



		qcom,core-freq = <240000000>;

		qcom,ahb-freq = <240000000>;
@@ -1612,6 +1615,7 @@ 
		clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>;

		clock-names = "xo";

		qcom,proxy-clock-names = "xo";

		qcom,mas-crypto = <&mas_crypto_c0>;



		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;