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Commit 1766e4b7 authored by Daniel Kurtz's avatar Daniel Kurtz Committed by Linus Walleij
Browse files

pinctrl/amd: fix gpio irq level in debugfs 



According to the AMD BKDG, the GPIO ActiveLevel bits (10:9) map to:
 00 Active High
 01 Active Low
 10 Active on both edges iff LevelTrig (bit 8) == 0
 11 Reserved

The current code has a bug where it interprets 00 => Active Low, and
01 => Active High.

Fix the bug, restrict "Active on both" to just the edge trigger case, and
refactor a bit to make the logic more readable.

Signed-off-by: default avatarDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 2e25a9cb

drivers/pinctrl/pinctrl-amd.c

+7 −7
Original line number Diff line number Diff line
@@ -247,16 +247,16 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 
			raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);



			if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {

				u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &

						ACTIVE_LEVEL_MASK;

				interrupt_enable = "interrupt is enabled|";



				if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&

				    !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))

					active_level = "Active low|";

				else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) &&

					 !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))

				if (level == ACTIVE_LEVEL_HIGH)

					active_level = "Active high|";

				else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&

					 pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))

				else if (level == ACTIVE_LEVEL_LOW)

					active_level = "Active low|";

				else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&

					 level == ACTIVE_LEVEL_BOTH)

					active_level = "Active on both|";

				else

					active_level = "Unknown Active level|";

drivers/pinctrl/pinctrl-amd.h

+4 −0
Original line number Diff line number Diff line
@@ -54,6 +54,10 @@ 
#define ACTIVE_LEVEL_MASK	0x3UL

#define DRV_STRENGTH_SEL_MASK	0x3UL



#define ACTIVE_LEVEL_HIGH	0x0UL

#define ACTIVE_LEVEL_LOW	0x1UL

#define ACTIVE_LEVEL_BOTH	0x2UL



#define DB_TYPE_NO_DEBOUNCE               0x0UL

#define DB_TYPE_PRESERVE_LOW_GLITCH       0x1UL

#define DB_TYPE_PRESERVE_HIGH_GLITCH      0x2UL