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Commit 2e25a9cb authored by Ludovic Barre's avatar Ludovic Barre Committed by Linus Walleij
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pinctrl: stm32: add syscfg mask parameter 



This patch adds mask parameter to define IRQ mux field.
This field could vary depend of IRQ mux selection register.
To avoid backward compatibility, the drivers set
the legacy value by default.

Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
Acked-by: default avatarAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent de1d08b2

drivers/pinctrl/stm32/pinctrl-stm32.c

+14 −2
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ 
#define STM32_GPIO_PINS_PER_BANK 16

#define STM32_GPIO_IRQ_LINE	 16



#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)



#define gpio_range_to_bank(chip) \

		container_of(chip, struct stm32_gpio_bank, range)
@@ -1054,6 +1056,7 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 
	struct device *dev = &pdev->dev;

	struct regmap *rm;

	int offset, ret, i;

	int mask, mask_width;



	parent = of_irq_find_parent(np);

	if (!parent)
@@ -1073,12 +1076,21 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 
	if (ret)

		return ret;



	ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);

	if (ret)

		mask = SYSCFG_IRQMUX_MASK;



	mask_width = fls(mask);



	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {

		struct reg_field mux;



		mux.reg = offset + (i / 4) * 4;

		mux.lsb = (i % 4) * 4;

		mux.msb = mux.lsb + 3;

		mux.lsb = (i % 4) * mask_width;

		mux.msb = mux.lsb + mask_width - 1;



		dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",

			i, mux.reg, mux.lsb, mux.msb);



		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);

		if (IS_ERR(pctl->irqmux[i]))