Merge "msm/sde/rotator: Snapshot of SDE Rotator supporting files" (11d619f5) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+9 −7

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
		*/

		#define pr_fmt(fmt) "msm-dsi-catalog:[%s] " fmt, __func__
		@@ -66,12 +66,12 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl,
		switch (version) {
		case DSI_CTRL_VERSION_1_4:
		ctrl->ops.setup_lane_map = dsi_ctrl_hw_14_setup_lane_map;
		ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_14_ulps_request;
		ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_14_ulps_exit;
		ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_cmn_ulps_request;
		ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_cmn_ulps_exit;
		ctrl->ops.wait_for_lane_idle =
		dsi_ctrl_hw_14_wait_for_lane_idle;
		ctrl->ops.ulps_ops.get_lanes_in_ulps =
		dsi_ctrl_hw_14_get_lanes_in_ulps;
		dsi_ctrl_hw_cmn_get_lanes_in_ulps;
		ctrl->ops.clamp_enable = dsi_ctrl_hw_14_clamp_enable;
		ctrl->ops.clamp_disable = dsi_ctrl_hw_14_clamp_disable;
		ctrl->ops.reg_dump_to_buffer =
		@@ -108,9 +108,10 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl,
		dsi_ctrl_hw_20_wait_for_lane_idle;
		ctrl->ops.reg_dump_to_buffer =
		dsi_ctrl_hw_20_reg_dump_to_buffer;
		ctrl->ops.ulps_ops.ulps_request = NULL;
		ctrl->ops.ulps_ops.ulps_exit = NULL;
		ctrl->ops.ulps_ops.get_lanes_in_ulps = NULL;
		ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_cmn_ulps_request;
		ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_cmn_ulps_exit;
		ctrl->ops.ulps_ops.get_lanes_in_ulps =
		dsi_ctrl_hw_cmn_get_lanes_in_ulps;
		ctrl->ops.clamp_enable = NULL;
		ctrl->ops.clamp_disable = NULL;
		ctrl->ops.schedule_dma_cmd = dsi_ctrl_hw_22_schedule_dma_cmd;
		@@ -188,6 +189,7 @@ static void dsi_catalog_phy_2_0_init(struct dsi_phy_hw *phy)
		phy->ops.calculate_timing_params =
		dsi_phy_hw_calculate_timing_params;
		phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v2_0;
		phy->ops.clamp_ctrl = dsi_phy_hw_v2_0_clamp_ctrl;
		}

		/**

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+5 −4

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
		*/

		#ifndef _DSI_CATALOG_H_
		@@ -77,6 +77,7 @@ void dsi_phy_hw_v2_0_idle_on(struct dsi_phy_hw phy, struct dsi_phy_cfg cfg);
		void dsi_phy_hw_v2_0_idle_off(struct dsi_phy_hw *phy);
		int dsi_phy_hw_timing_val_v2_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
		u32 *timing_val, u32 size);
		void dsi_phy_hw_v2_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable);

		/* Definitions for 10nm PHY hardware driver */
		void dsi_phy_hw_v3_0_regulator_enable(struct dsi_phy_hw *phy,
		@@ -205,9 +206,9 @@ int dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl_hw *ctrl);
		int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);
		void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl,
		struct dsi_lane_map *lane_map);
		void dsi_ctrl_hw_14_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes);
		void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes);
		u32 dsi_ctrl_hw_14_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl);
		void dsi_ctrl_hw_cmn_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes);
		void dsi_ctrl_hw_cmn_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes);
		u32 dsi_ctrl_hw_cmn_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl);

		void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl,
		u32 lanes,

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+22 −7

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
		*/

		#define pr_fmt(fmt) "dsi-ctrl:[%s] " fmt, __func__
		@@ -32,6 +32,9 @@
		#define TO_ON_OFF(x) ((x) ? "ON" : "OFF")

		#define CEIL(x, y) (((x) + ((y)-1)) / (y))

		#define TICKS_IN_MICRO_SECOND 1000000

		/**
		* enum dsi_ctrl_driver_ops - controller driver ops
		*/
		@@ -412,9 +415,9 @@ bool dsi_ctrl_validate_host_state(struct dsi_ctrl *dsi_ctrl)
		}

		if (!state->host_initialized)
		return true;

		return false;

		return true;
		}

		static void dsi_ctrl_update_state(struct dsi_ctrl *dsi_ctrl,
		@@ -822,7 +825,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
		{
		int rc = 0;
		u32 num_of_lanes = 0;
		u32 bpp;
		u32 bpp, refresh_rate = TICKS_IN_MICRO_SECOND;
		u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,
		byte_clk_rate;
		struct dsi_host_common_cfg *host_cfg = &config->common_config;
		@@ -840,12 +843,18 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
		if (host_cfg->data_lanes & DSI_DATA_LANE_3)
		num_of_lanes++;

		if (config->bit_clk_rate_hz == 0) {
		if (config->bit_clk_rate_hz_override == 0) {
		h_period = DSI_H_TOTAL_DSC(timing);
		v_period = DSI_V_TOTAL(timing);
		bit_rate = h_period * v_period * timing->refresh_rate * bpp;

		if (config->panel_mode == DSI_OP_CMD_MODE)
		do_div(refresh_rate, timing->mdp_transfer_time_us);
		else
		refresh_rate = timing->refresh_rate;

		bit_rate = h_period * v_period * refresh_rate * bpp;
		} else {
		bit_rate = config->bit_clk_rate_hz * num_of_lanes;
		bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;
		}

		bit_rate_per_lane = bit_rate;
		@@ -862,6 +871,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
		dsi_ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
		dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;
		dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;
		config->bit_clk_rate_hz = dsi_ctrl->clk_freq.byte_clk_rate * 8;

		rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,
		dsi_ctrl->cell_index);
		@@ -1186,6 +1196,11 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl,
		}

		kickoff:
		/* check if custom dma scheduling line needed */
		if ((dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) &&
		(flags & DSI_CTRL_CMD_CUSTOM_DMA_SCHED))
		line_no = dsi_ctrl->host_config.u.video_engine.dma_sched_line;

		timing = &(dsi_ctrl->host_config.video_timing);
		if (timing)
		line_no += timing->v_back_porch + timing->v_sync_width +

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h

+4 −1

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
		*/

		#ifndef _DSI_CTRL_H_
		@@ -29,6 +29,8 @@
		* @DSI_CTRL_CMD_LAST_COMMAND: Trigger the DMA cmd transfer if this is last
		* command in the batch.
		* @DSI_CTRL_CMD_NON_EMBEDDED_MODE:Transfer cmd packets in non embedded mode.
		* @DSI_CTRL_CMD_CUSTOM_DMA_SCHED: Use the dma scheduling line number defined in
		* display panel dtsi file instead of default.
		*/
		#define DSI_CTRL_CMD_READ 0x1
		#define DSI_CTRL_CMD_BROADCAST 0x2
		@@ -38,6 +40,7 @@
		#define DSI_CTRL_CMD_FETCH_MEMORY 0x20
		#define DSI_CTRL_CMD_LAST_COMMAND 0x40
		#define DSI_CTRL_CMD_NON_EMBEDDED_MODE 0x80
		#define DSI_CTRL_CMD_CUSTOM_DMA_SCHED 0x100

		/* DSI embedded mode fifo size
		* If the command is greater than 256 bytes it is sent in non-embedded mode.

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c

+17 −9

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
		*/

		#define pr_fmt(fmt) "dsi-hw:" fmt
		@@ -99,12 +99,14 @@ int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes)
		* Caller should check if lanes are in ULPS mode by calling
		* get_lanes_in_ulps() operation.
		*/
		void dsi_ctrl_hw_14_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes)
		void dsi_ctrl_hw_cmn_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes)
		{
		u32 reg = 0;

		reg = DSI_R32(ctrl, DSI_LANE_CTRL);

		if (lanes & DSI_CLOCK_LANE)
		reg = BIT(4);
		reg \|= BIT(4);
		if (lanes & DSI_DATA_LANE_0)
		reg \|= BIT(0);
		if (lanes & DSI_DATA_LANE_1)
		@@ -134,12 +136,16 @@ void dsi_ctrl_hw_14_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes)
		* Caller should check if lanes are in active mode by calling
		* get_lanes_in_ulps() operation.
		*/
		void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
		void dsi_ctrl_hw_cmn_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
		{
		u32 reg = 0;
		u32 prev_reg = 0;

		prev_reg = DSI_R32(ctrl, DSI_LANE_CTRL);
		prev_reg &= BIT(24);

		if (lanes & DSI_CLOCK_LANE)
		reg = BIT(12);
		reg \|= BIT(12);
		if (lanes & DSI_DATA_LANE_0)
		reg \|= BIT(8);
		if (lanes & DSI_DATA_LANE_1)
		@@ -153,7 +159,7 @@ void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
		* ULPS Exit Request
		* Hardware requirement is to wait for at least 1ms
		*/
		DSI_W32(ctrl, DSI_LANE_CTRL, reg);
		DSI_W32(ctrl, DSI_LANE_CTRL, reg \| prev_reg);
		usleep_range(1000, 1010);
		/*
		* Sometimes when exiting ULPS, it is possible that some DSI
		@@ -161,8 +167,10 @@ void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
		* commands not going through. To avoid this, force the lanes
		* to be in stop state.
		*/
		DSI_W32(ctrl, DSI_LANE_CTRL, reg << 8);
		DSI_W32(ctrl, DSI_LANE_CTRL, 0x0);
		DSI_W32(ctrl, DSI_LANE_CTRL, (reg << 8) \| prev_reg);
		wmb(); /* ensure lanes are put to stop state */
		DSI_W32(ctrl, DSI_LANE_CTRL, 0x0 \| prev_reg);
		wmb(); /* ensure lanes are put to stop state */

		pr_debug("[DSI_%d] ULPS exit request for lanes=0x%x\n",
		ctrl->index, lanes);
		@@ -177,7 +185,7 @@ void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
		*
		* Return: List of lanes in ULPS state.
		*/
		u32 dsi_ctrl_hw_14_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl)
		u32 dsi_ctrl_hw_cmn_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl)
		{
		u32 reg = 0;
		u32 lanes = 0;