mmc: core: set REL_WR_SEC_C register to 0x1 per eMMC5.0 spec

Some eMMC vendors violate eMMC 5.0 spec and set REL_WR_SEC_C
register to 0x10 to indicate the ability of RPMB throughput
improvement thus lead to failure when TZ module write data to
RPMB partition. This change will check bit[4] of EXT_CSD[166]
and if it is not set then change value of REL_WR_SEC_C to 0x1
directly ignoring value of EXT_CSD[222].

Change-Id: I52d1c612017eb56153f667502faaf76bc0c1bcc0
Signed-off-by: xiaonian <xiaonian@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
Signed-off-by: Ram Prakash Gupta <rampraka@codeaurora.org>