usb: dwc3-msm-core: Set pipectl susphy in conndone interrupt

As per DesignWare Cores SuperSpeed USB 3.0 Controller Databook
Version 3.00a May 2015, section 8.1.3: Initialization on Connect
Done (Step-4)

GUSB2CFG/ GUSB3PIPECTL:
Depending on the connected speed, write to the other PHY’s control
register to suspend it

For SMMU Fault issue where the controller was accessing 0th address,
as per tests conducted, during core initialization, if the
GUSB3PIPECTL SUSPHY bit is set, the register writes (including GEVT)
are not going through and causing a CSR Timeout. As per databook, the
USB3 SUSPHY bit must be enabled after the link up happens in high
speed and not during core initialization. Fix this by clearing the
bit before core soft reset and setting it in conndone exit kretprobe
if the link up happens in high speed.

Change-Id: I6d416545220f65064a17248f1b1ba5a3a0a7eac2
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>