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Commit 03a0a3e5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2018-05-09' of... 

Merge tag 'drm-intel-fixes-2018-05-09' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

- Increase LVDS panel timeout to 5s to avoid spurious *ERROR*
- Fix 2 WARNS: BIOS framebuffer related (FDO #105992) and eDP cdclk mismatch

* tag 'drm-intel-fixes-2018-05-09' of git://anongit.freedesktop.org/drm/drm-intel:
  drm/i915: Fix drm:intel_enable_lvds ERROR message in kernel log
  drm/i915: Correctly populate user mode h/vdisplay with pipe src size during readout
  drm/i915: Adjust eDP's logical vco in a reliable place.
parents 87bf742b e8f48f96

drivers/gpu/drm/i915/intel_cdclk.c

+37 −4
Original line number Diff line number Diff line
@@ -2302,9 +2302,44 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) 
	return 0;

}



static int skl_dpll0_vco(struct intel_atomic_state *intel_state)

{

	struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);

	struct intel_crtc *crtc;

	struct intel_crtc_state *crtc_state;

	int vco, i;



	vco = intel_state->cdclk.logical.vco;

	if (!vco)

		vco = dev_priv->skl_preferred_vco_freq;



	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {

		if (!crtc_state->base.enable)

			continue;



		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))

			continue;



		/*

		 * DPLL0 VCO may need to be adjusted to get the correct

		 * clock for eDP. This will affect cdclk as well.

		 */

		switch (crtc_state->port_clock / 2) {

		case 108000:

		case 216000:

			vco = 8640000;

			break;

		default:

			vco = 8100000;

			break;

		}

	}



	return vco;

}



static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)

{

	struct drm_i915_private *dev_priv = to_i915(state->dev);

	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);

	int min_cdclk, cdclk, vco;
@@ -2312,9 +2347,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) 
	if (min_cdclk < 0)

		return min_cdclk;



	vco = intel_state->cdclk.logical.vco;

	if (!vco)

		vco = dev_priv->skl_preferred_vco_freq;

	vco = skl_dpll0_vco(intel_state);



	/*

	 * FIXME should also account for plane ratio

drivers/gpu/drm/i915/intel_display.c

+2 −0
Original line number Diff line number Diff line
@@ -15178,6 +15178,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) 
		memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));

		if (crtc_state->base.active) {

			intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);

			crtc->base.mode.hdisplay = crtc_state->pipe_src_w;

			crtc->base.mode.vdisplay = crtc_state->pipe_src_h;

			intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);

			WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));

drivers/gpu/drm/i915/intel_dp.c

+0 −20
Original line number Diff line number Diff line
@@ -1881,26 +1881,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
				reduce_m_n);

	}



	/*

	 * DPLL0 VCO may need to be adjusted to get the correct

	 * clock for eDP. This will affect cdclk as well.

	 */

	if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {

		int vco;



		switch (pipe_config->port_clock / 2) {

		case 108000:

		case 216000:

			vco = 8640000;

			break;

		default:

			vco = 8100000;

			break;

		}



		to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;

	}



	if (!HAS_DDI(dev_priv))

		intel_dp_set_clock(encoder, pipe_config);

drivers/gpu/drm/i915/intel_lvds.c

+2 −1
Original line number Diff line number Diff line
@@ -326,7 +326,8 @@ static void intel_enable_lvds(struct intel_encoder *encoder, 


	I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);

	POSTING_READ(lvds_encoder->reg);

	if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))



	if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))

		DRM_ERROR("timed out waiting for panel to power on\n");



	intel_panel_enable_backlight(pipe_config, conn_state);