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Commit 03752148 authored by Roger Quadros's avatar Roger Quadros Committed by Tony Lindgren
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ARM: dts: am335x: Fix NAND device nodes



Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.

Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent cb9ea8b6
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+5 −1
Original line number Original line Diff line number Diff line
@@ -236,7 +236,11 @@
	status = "okay";
	status = "okay";


	nand@0,0 {
	nand@0,0 {
		reg = <0 0 0>; /* CS0, offset 0 */
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		nand-bus-width = <8>;
		nand-bus-width = <8>;
		ti,nand-ecc-opt = "bch8";
		ti,nand-ecc-opt = "bch8";
		ti,nand-xfer-type = "polled";
		ti,nand-xfer-type = "polled";
+5 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,7 @@
 * published by the Free Software Foundation.
 * published by the Free Software Foundation.
 */
 */
#include "am33xx.dtsi"
#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>


/ {
/ {
	model = "Grinn AM335x ChiliSOM";
	model = "Grinn AM335x ChiliSOM";
@@ -218,7 +219,11 @@
	pinctrl-0 = <&nandflash_pins>;
	pinctrl-0 = <&nandflash_pins>;
	ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
	ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
	nand@0,0 {
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		ti,nand-ecc-opt = "bch8";
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		ti,elm-id = <&elm>;
		nand-bus-width = <8>;
		nand-bus-width = <8>;
+6 −1
Original line number Original line Diff line number Diff line
@@ -11,6 +11,7 @@
/dts-v1/;
/dts-v1/;


#include "am33xx.dtsi"
#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>


/ {
/ {
	model = "CompuLab CM-T335";
	model = "CompuLab CM-T335";
@@ -302,7 +303,11 @@ status = "okay";
	pinctrl-0 = <&nandflash_pins>;
	pinctrl-0 = <&nandflash_pins>;
	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
	nand@0,0 {
	nand@0,0 {
		reg = <0 0 0>; /* CS0, offset 0 */
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		ti,nand-ecc-opt = "bch8";
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		ti,elm-id = <&elm>;
		nand-bus-width = <8>;
		nand-bus-width = <8>;
+4 −0
Original line number Original line Diff line number Diff line
@@ -519,7 +519,11 @@
	pinctrl-0 = <&nandflash_pins_s0>;
	pinctrl-0 = <&nandflash_pins_s0>;
	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
	nand@0,0 {
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		ti,nand-ecc-opt = "bch8";
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		ti,elm-id = <&elm>;
		nand-bus-width = <8>;
		nand-bus-width = <8>;
+5 −0
Original line number Original line Diff line number Diff line
@@ -11,6 +11,7 @@
/dts-v1/;
/dts-v1/;


#include "am33xx.dtsi"
#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>


/ {
/ {
	cpus {
	cpus {
@@ -129,7 +130,11 @@
	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */


	nand@0,0 {
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		nand-bus-width = <8>;
		nand-bus-width = <8>;
		ti,nand-ecc-opt = "bch8";
		ti,nand-ecc-opt = "bch8";
		gpmc,device-width = <1>;
		gpmc,device-width = <1>;
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