Commit 030999fe authored Jul 25, 2017 by Peter De Schrijver Committed by Stephen Boyd Aug 23, 2017

clk: tegra: disable SSC for PLL_D2



PLLD2 is used for HDMI which does not allow Spread Spectrum clocking.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

parent 04434cfa

drivers/clk/tegra/clk-tegra210.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -146,7 +146,7 @@
		#define PLLD_SDM_EN_MASK BIT(16)

		#define PLLD2_SDM_EN_MASK BIT(31)
		#define PLLD2_SSC_EN_MASK BIT(30)
		#define PLLD2_SSC_EN_MASK 0

		#define PLLDP_SS_CFG 0x598
		#define PLLDP_SDM_EN_MASK BIT(31)