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Commit fff4496e authored by Richard Schleich's avatar Richard Schleich Committed by Greg Kroah-Hartman
Browse files

ARM: dts: bcm2837: Add the missing L1/L2 cache information 



[ Upstream commit bdf8762da268d2a34abf517c36528413906e9cd5 ]

This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2837 on newer kernel versions.

Signed-off-by: default avatarRichard Schleich <rs@noreya.tech>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
[florian: Align and remove comments matching property values]
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 09cee455

arch/arm64/boot/dts/broadcom/bcm2837.dtsi

+49 −0
Original line number Diff line number Diff line
@@ -31,12 +31,26 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		/* Source for d/i-cache-line-size and d/i-cache-sets

		 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system

		 * /about-the-l1-memory-system?lang=en

		 *

		 * Source for d/i-cache-size

		 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks

		 */

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000d8>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			next-level-cache = <&l2>;

		};



		cpu1: cpu@1 {
@@ -45,6 +59,13 @@ 
			reg = <1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000e0>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			next-level-cache = <&l2>;

		};



		cpu2: cpu@2 {
@@ -53,6 +74,13 @@ 
			reg = <2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000e8>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			next-level-cache = <&l2>;

		};



		cpu3: cpu@3 {
@@ -61,6 +89,27 @@ 
			reg = <3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000f0>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			next-level-cache = <&l2>;

		};



		/* Source for cache-line-size + cache-sets

		 * https://developer.arm.com/documentation/ddi0500

		 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en

		 * Source for cache-size

		 * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf

		 */

		l2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set

			cache-level = <2>;

		};

	};

};