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Commit ff8ce5f6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm 

Pull core ARM updates from Russell King:
 "This is the bulk of the core ARM updates for this merge window.
  Included in here is a different way to handle the VIVT cache flushing
  on context switch, which should allow scheduler folk to remove a
  special case in their core code.

  We have architectured timer support here, which is a set of timers
  specified by the ARM architecture for future SoCs.  So we should see
  less variability in timer design going forward.

  The last big thing here is my cleanup to the way we handle PCI across
  ARM, fixing some oddities in some platforms which hadn't realised
  there was a way to deal with their private data already built in to
  our PCI backend.

  I've also removed support for the ARMv3 architecture; it hasn't worked
  properly for years so it seems pointless to keep it around."

* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (47 commits)
  ARM: PCI: remove per-pci_hw list of buses
  ARM: PCI: dove/kirkwood/mv78xx0: use sys->private_data
  ARM: PCI: provide a default bus scan implementation
  ARM: PCI: get rid of pci_std_swizzle()
  ARM: PCI: versatile: fix PCI interrupt setup
  ARM: PCI: integrator: use common PCI swizzle
  ARM: 7416/1: LPAE: Remove unused L_PTE_(BUFFERABLE|CACHEABLE) macros
  ARM: 7415/1: vfp: convert printk's to pr_*'s
  ARM: decompressor: avoid speculative prefetch from non-RAM areas
  ARM: Remove ARMv3 support from decompressor
  ARM: 7413/1: move read_{boot,persistent}_clock to the architecture level
  ARM: Remove support for ARMv3 ARM610 and ARM710 CPUs
  ARM: 7363/1: DEBUG_LL: limit early mapping to the minimum
  ARM: 7391/1: versatile: add some auxdata for device trees
  ARM: 7389/2: plat-versatile: modernize FPGA IRQ controller
  AMBA: get rid of last two uses of NO_IRQ
  ARM: 7408/1: cacheflush: return error to userspace when flushing syscall fails
  ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
  ARM: 7404/1: cmpxchg64: use atomic64 and local64 routines for cmpxchg64
  ARM: 7347/1: SCU: use cpu_logical_map for per-CPU low power mode
  ...
parents 4f6ade91 4ab10567

Documentation/devicetree/bindings/arm/arch_timer.txt

0 → 100644
+27 −0
Original line number Diff line number Diff line 
* ARM architected timer



ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which

provides per-cpu timers.



The timer is attached to a GIC to deliver its per-processor interrupts.



** Timer node properties:



- compatible : Should at least contain "arm,armv7-timer".



- interrupts : Interrupt list for secure, non-secure, virtual and

  hypervisor timers, in that order.



- clock-frequency : The frequency of the main counter, in Hz. Optional.



Example:



	timer {

		compatible = "arm,cortex-a15-timer",

			     "arm,armv7-timer";

		interrupts = <1 13 0xf08>,

			     <1 14 0xf08>,

			     <1 11 0xf08>,

			     <1 10 0xf08>;

		clock-frequency = <100000000>;

	};

arch/arm/Kconfig

+10 −12
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ config ARM 
	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)

	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL

	select HAVE_ARCH_KGDB

	select HAVE_ARCH_TRACEHOOK

	select HAVE_KPROBES if !XIP_KERNEL

	select HAVE_KRETPROBES if (HAVE_KPROBES)

	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
@@ -30,6 +31,8 @@ config ARM 
	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))

	select HAVE_C_RECORDMCOUNT

	select HAVE_GENERIC_HARDIRQS

	select HARDIRQS_SW_RESEND

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

	select CPU_PM if (SUSPEND || CPU_IDLE)

	select GENERIC_PCI_IOMAP
@@ -126,14 +129,6 @@ config TRACE_IRQFLAGS_SUPPORT 
	bool

	default y



config HARDIRQS_SW_RESEND

	bool

	default y



config GENERIC_IRQ_PROBE

	bool

	default y



config GENERIC_LOCKBREAK

	bool

	default y
@@ -280,6 +275,7 @@ config ARCH_INTEGRATOR 
	select NEED_MACH_IO_H

	select NEED_MACH_MEMORY_H

	select SPARSE_IRQ

	select MULTI_IRQ_HANDLER

	help

	  Support for ARM's Integrator platform.
@@ -632,7 +628,6 @@ config ARCH_MMP 
	select CLKDEV_LOOKUP

	select GENERIC_CLOCKEVENTS

	select GPIO_PXA

	select TICK_ONESHOT

	select PLAT_PXA

	select SPARSE_IRQ

	select GENERIC_ALLOCATOR
@@ -716,7 +711,6 @@ config ARCH_PXA 
	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_CLOCKEVENTS

	select GPIO_PXA

	select TICK_ONESHOT

	select PLAT_PXA

	select SPARSE_IRQ

	select AUTO_ZRELADDR
@@ -783,7 +777,6 @@ config ARCH_SA1100 
	select CPU_FREQ

	select GENERIC_CLOCKEVENTS

	select CLKDEV_LOOKUP

	select TICK_ONESHOT

	select ARCH_REQUIRE_GPIOLIB

	select HAVE_IDE

	select NEED_MACH_MEMORY_H
@@ -1552,10 +1545,15 @@ config HAVE_ARM_SCU 
	help

	  This option enables support for the ARM system coherency unit



config ARM_ARCH_TIMER

	bool "Architected timer support"

	depends on CPU_V7

	help

	  This option enables support for the ARM architected timer



config HAVE_ARM_TWD

	bool

	depends on SMP

	select TICK_ONESHOT

	help

	  This options enables support for the ARM timer and watchdog unit

arch/arm/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -70,8 +70,6 @@ arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4 
arch-$(CONFIG_CPU_32v3)		:=-D__LINUX_ARM_ARCH__=3 -march=armv3



# This selects how we optimise for the processor.

tune-$(CONFIG_CPU_ARM610)	:=-mtune=arm610

tune-$(CONFIG_CPU_ARM710)	:=-mtune=arm710

tune-$(CONFIG_CPU_ARM7TDMI)	:=-mtune=arm7tdmi

tune-$(CONFIG_CPU_ARM720T)	:=-mtune=arm7tdmi

tune-$(CONFIG_CPU_ARM740T)	:=-mtune=arm7tdmi

arch/arm/boot/compressed/head.S

+21 −50
Original line number Diff line number Diff line
@@ -567,6 +567,12 @@ __armv3_mpu_cache_on: 
		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3

		mov	pc, lr



#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

#define CB_BITS 0x08

#else

#define CB_BITS 0x0c

#endif



__setup_mmu:	sub	r3, r4, #16384		@ Page directory size

		bic	r3, r3, #0xff		@ Align the pointer

		bic	r3, r3, #0x3f00
@@ -578,17 +584,14 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size 
		mov	r9, r0, lsr #18

		mov	r9, r9, lsl #18		@ start of RAM

		add	r10, r9, #0x10000000	@ a reasonable RAM size

		mov	r1, #0x12

		orr	r1, r1, #3 << 10

		mov	r1, #0x12		@ XN|U + section mapping

		orr	r1, r1, #3 << 10	@ AP=11

		add	r2, r3, #16384

1:		cmp	r1, r9			@ if virt > start of RAM

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

		orrhs	r1, r1, #0x08		@ set cacheable

#else

		orrhs	r1, r1, #0x0c		@ set cacheable, bufferable

#endif

		cmp	r1, r10			@ if virt > end of RAM

		bichs	r1, r1, #0x0c		@ clear cacheable, bufferable

		cmphs	r10, r1			@   && end of RAM > virt

		bic	r1, r1, #0x1c		@ clear XN|U + C + B

		orrlo	r1, r1, #0x10		@ Set XN|U for non-RAM

		orrhs	r1, r1, r6		@ set RAM section settings

		str	r1, [r0], #4		@ 1:1 mapping

		add	r1, r1, #1048576

		teq	r0, r2
@@ -599,7 +602,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size 
 * so there is no map overlap problem for up to 1 MB compressed kernel.

 * If the execution is in RAM then we would only be duplicating the above.

 */

		mov	r1, #0x1e

		orr	r1, r6, #0x04		@ ensure B is set for this

		orr	r1, r1, #3 << 10

		mov	r2, pc

		mov	r2, r2, lsr #20
@@ -620,6 +623,7 @@ __arm926ejs_mmu_cache_on: 
__armv4_mmu_cache_on:

		mov	r12, lr

#ifdef CONFIG_MMU

		mov	r6, #CB_BITS | 0x12	@ U

		bl	__setup_mmu

		mov	r0, #0

		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
@@ -641,6 +645,7 @@ __armv7_mmu_cache_on: 
#ifdef CONFIG_MMU

		mrc	p15, 0, r11, c0, c1, 4	@ read ID_MMFR0

		tst	r11, #0xf		@ VMSA

		movne	r6, #CB_BITS | 0x02	@ !XN

		blne	__setup_mmu

		mov	r0, #0

		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
@@ -655,7 +660,7 @@ __armv7_mmu_cache_on: 
		orr	r0, r0, #1 << 25	@ big-endian page tables

#endif

		orrne	r0, r0, #1		@ MMU enabled

		movne	r1, #-1

		movne	r1, #0xfffffffd		@ domain 0 = client

		mcrne	p15, 0, r3, c2, c0, 0	@ load page table pointer

		mcrne	p15, 0, r1, c3, c0, 0	@ load domain access control

#endif
@@ -668,6 +673,7 @@ __armv7_mmu_cache_on: 


__fa526_cache_on:

		mov	r12, lr

		mov	r6, #CB_BITS | 0x12	@ U

		bl	__setup_mmu

		mov	r0, #0

		mcr	p15, 0, r0, c7, c7, 0	@ Invalidate whole cache
@@ -680,18 +686,6 @@ __fa526_cache_on: 
		mcr	p15, 0, r0, c8, c7, 0	@ flush UTLB

		mov	pc, r12



__arm6_mmu_cache_on:

		mov	r12, lr

		bl	__setup_mmu

		mov	r0, #0

		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3

		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3

		mov	r0, #0x30

		bl	__common_mmu_cache_on

		mov	r0, #0

		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3

		mov	pc, r12



__common_mmu_cache_on:

#ifndef CONFIG_THUMB2_KERNEL

#ifndef DEBUG
@@ -756,16 +750,6 @@ call_cache_fn: adr r12, proc_types 
		.align	2

		.type	proc_types,#object

proc_types:

		.word	0x41560600		@ ARM6/610

		.word	0xffffffe0

		W(b)	__arm6_mmu_cache_off	@ works, but slow

		W(b)	__arm6_mmu_cache_off

		mov	pc, lr

 THUMB(		nop				)

@		b	__arm6_mmu_cache_on		@ untested

@		b	__arm6_mmu_cache_off

@		b	__armv3_mmu_cache_flush



		.word	0x00000000		@ old ARM ID

		.word	0x0000f000

		mov	pc, lr
@@ -777,8 +761,10 @@ proc_types: 


		.word	0x41007000		@ ARM7/710

		.word	0xfff8fe00

		W(b)	__arm7_mmu_cache_off

		W(b)	__arm7_mmu_cache_off

		mov	pc, lr

 THUMB(		nop				)

		mov	pc, lr

 THUMB(		nop				)

		mov	pc, lr

 THUMB(		nop				)
@@ -977,21 +963,6 @@ __armv7_mmu_cache_off: 
		mcr	p15, 0, r0, c7, c5, 4	@ ISB

		mov	pc, r12



__arm6_mmu_cache_off:

		mov	r0, #0x00000030		@ ARM6 control reg.

		b	__armv3_mmu_cache_off



__arm7_mmu_cache_off:

		mov	r0, #0x00000070		@ ARM7 control reg.

		b	__armv3_mmu_cache_off



__armv3_mmu_cache_off:

		mcr	p15, 0, r0, c1, c0, 0	@ turn MMU and cache off

		mov	r0, #0

		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3

		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3

		mov	pc, lr



/*

 * Clean and flush the cache to maintain consistency.

 *

arch/arm/common/it8152.c

+1 −6
Original line number Diff line number Diff line
@@ -222,7 +222,7 @@ static int it8152_pci_write_config(struct pci_bus *bus, 
	return PCIBIOS_SUCCESSFUL;

}



static struct pci_ops it8152_ops = {

struct pci_ops it8152_ops = {

	.read = it8152_pci_read_config,

	.write = it8152_pci_write_config,

};
@@ -346,9 +346,4 @@ void pcibios_set_master(struct pci_dev *dev) 
}





struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)

{

	return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources);

}



EXPORT_SYMBOL(dma_set_coherent_mask);