Merge branch 'v3-removal' into for-linus (4ab10567) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm/Makefile

+0 −2

Original line number	Diff line number	Diff line
		@@ -70,8 +70,6 @@ arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4
		arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3

		# This selects how we optimise for the processor.
		tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610
		tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710
		tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi
		tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi
		tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi

arch/arm/boot/compressed/head.S

+4 −40

Original line number	Diff line number	Diff line
		@@ -686,19 +686,6 @@ __fa526_cache_on:
		mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
		mov pc, r12

		__arm6_mmu_cache_on:
		mov r12, lr
		mov r6, #CB_BITS \| 0x12 @ U
		bl __setup_mmu
		mov r0, #0
		mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
		mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
		mov r0, #0x30
		bl __common_mmu_cache_on
		mov r0, #0
		mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
		mov pc, r12

		__common_mmu_cache_on:
		#ifndef CONFIG_THUMB2_KERNEL
		#ifndef DEBUG
		@@ -763,16 +750,6 @@ call_cache_fn: adr r12, proc_types
		.align 2
		.type proc_types,#object
		proc_types:
		.word 0x41560600 @ ARM6/610
		.word 0xffffffe0
		W(b) __arm6_mmu_cache_off @ works, but slow
		W(b) __arm6_mmu_cache_off
		mov pc, lr
		THUMB( nop )
		@ b __arm6_mmu_cache_on @ untested
		@ b __arm6_mmu_cache_off
		@ b __armv3_mmu_cache_flush

		.word 0x00000000 @ old ARM ID
		.word 0x0000f000
		mov pc, lr
		@@ -784,8 +761,10 @@ proc_types:

		.word 0x41007000 @ ARM7/710
		.word 0xfff8fe00
		W(b) __arm7_mmu_cache_off
		W(b) __arm7_mmu_cache_off
		mov pc, lr
		THUMB( nop )
		mov pc, lr
		THUMB( nop )
		mov pc, lr
		THUMB( nop )

		@@ -984,21 +963,6 @@ __armv7_mmu_cache_off:
		mcr p15, 0, r0, c7, c5, 4 @ ISB
		mov pc, r12

		__arm6_mmu_cache_off:
		mov r0, #0x00000030 @ ARM6 control reg.
		b __armv3_mmu_cache_off

		__arm7_mmu_cache_off:
		mov r0, #0x00000070 @ ARM7 control reg.
		b __armv3_mmu_cache_off

		__armv3_mmu_cache_off:
		mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
		mov r0, #0
		mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
		mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
		mov pc, lr

		/*
		* Clean and flush the cache to maintain consistency.
		*

arch/arm/configs/rpc_defconfig

+0 −2

Original line number	Diff line number	Diff line
		@@ -8,8 +8,6 @@ CONFIG_MODULES=y
		CONFIG_MODULE_UNLOAD=y
		# CONFIG_BLK_DEV_BSG is not set
		CONFIG_ARCH_RPC=y
		CONFIG_CPU_ARM610=y
		CONFIG_CPU_ARM710=y
		CONFIG_CPU_SA110=y
		CONFIG_ZBOOT_ROM_TEXT=0x0
		CONFIG_ZBOOT_ROM_BSS=0x0

arch/arm/include/asm/glue-df.h

+0 −8

Original line number	Diff line number	Diff line
		@@ -31,14 +31,6 @@
		#undef CPU_DABORT_HANDLER
		#undef MULTI_DABORT

		#if defined(CONFIG_CPU_ARM610)
		# ifdef CPU_DABORT_HANDLER
		# define MULTI_DABORT 1
		# else
		# define CPU_DABORT_HANDLER cpu_arm6_data_abort
		# endif
		#endif

		#if defined(CONFIG_CPU_ARM710)
		# ifdef CPU_DABORT_HANDLER
		# define MULTI_DABORT 1

arch/arm/include/asm/glue-proc.h

+0 −18

Original line number	Diff line number	Diff line
		@@ -23,15 +23,6 @@
		* CPU_NAME - the prefix for CPU related functions
		*/

		#ifdef CONFIG_CPU_ARM610
		# ifdef CPU_NAME
		# undef MULTI_CPU
		# define MULTI_CPU
		# else
		# define CPU_NAME cpu_arm6
		# endif
		#endif

		#ifdef CONFIG_CPU_ARM7TDMI
		# ifdef CPU_NAME
		# undef MULTI_CPU
		@@ -41,15 +32,6 @@
		# endif
		#endif

		#ifdef CONFIG_CPU_ARM710
		# ifdef CPU_NAME
		# undef MULTI_CPU
		# define MULTI_CPU
		# else
		# define CPU_NAME cpu_arm7
		# endif
		#endif

		#ifdef CONFIG_CPU_ARM720T
		# ifdef CPU_NAME
		# undef MULTI_CPU