Loading drivers/soc/qcom/llcc-core.c +11 −1 Original line number Diff line number Diff line Loading @@ -35,6 +35,15 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 #ifdef CONFIG_EDAC_QCOM_LLCC #define ENABLE_ECC_INTR 1 #else #define ENABLE_ECC_INTR 0 #endif static int enable_ecc_intr = ENABLE_ECC_INTR; module_param(enable_ecc_intr, int, 0444); static void qcom_llcc_core_setup(struct regmap *llcc_regmap, uint32_t b_off) { u32 sb_err_threshold; Loading Loading @@ -81,6 +90,7 @@ static int qcom_llcc_core_probe(struct platform_device *pdev) return -EINVAL; } if (enable_ecc_intr) qcom_llcc_core_setup(llcc_regmap, b_off); return 0; Loading Loading
drivers/soc/qcom/llcc-core.c +11 −1 Original line number Diff line number Diff line Loading @@ -35,6 +35,15 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 #ifdef CONFIG_EDAC_QCOM_LLCC #define ENABLE_ECC_INTR 1 #else #define ENABLE_ECC_INTR 0 #endif static int enable_ecc_intr = ENABLE_ECC_INTR; module_param(enable_ecc_intr, int, 0444); static void qcom_llcc_core_setup(struct regmap *llcc_regmap, uint32_t b_off) { u32 sb_err_threshold; Loading Loading @@ -81,6 +90,7 @@ static int qcom_llcc_core_probe(struct platform_device *pdev) return -EINVAL; } if (enable_ecc_intr) qcom_llcc_core_setup(llcc_regmap, b_off); return 0; Loading