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Commit 61abfd3b authored by Channagoud Kadabi's avatar Channagoud Kadabi
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soc: qcom: Conditionally enable ecc interrupt config 



Due to security reasons the ECC registers cannot be accessed from HLOS.
Enable ecc interrupts for LLCC only when edac driver for llcc is
enabled.

Change-Id: I3278034da5485ec918c8be8368ffa986642d40ee
Signed-off-by: default avatarChannagoud Kadabi <ckadabi@codeaurora.org>
parent 5bc5bb65

drivers/soc/qcom/llcc-core.c

+11 −1
Original line number Diff line number Diff line
@@ -35,6 +35,15 @@ 
#define DRP0_INTERRUPT_ENABLE	BIT(6)

#define SB_DB_DRP_INTERRUPT_ENABLE	0x3



#ifdef CONFIG_EDAC_QCOM_LLCC

#define ENABLE_ECC_INTR 1

#else

#define ENABLE_ECC_INTR 0

#endif



static int enable_ecc_intr = ENABLE_ECC_INTR;

module_param(enable_ecc_intr, int, 0444);



static void qcom_llcc_core_setup(struct regmap *llcc_regmap, uint32_t b_off)

{

	u32 sb_err_threshold;
@@ -81,6 +90,7 @@ static int qcom_llcc_core_probe(struct platform_device *pdev) 
		return -EINVAL;

	}



	if (enable_ecc_intr)

		qcom_llcc_core_setup(llcc_regmap, b_off);



	return 0;