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Commit fb98c2d1 authored by Vicky Wallace's avatar Vicky Wallace
Browse files

clk: qcom: Remove gpu_cc_ahb_clk for SDM845 



Remove the clock from the HLOS control. This allow
the clock can be shared with other client. It's
left at default state as enabled.

CRs-Fixed: 2128570
Change-Id: I185cf42ffae529df1251c13a881d7be4af12664b
Signed-off-by: default avatarVicky Wallace <vwallace@codeaurora.org>
parent c55afbaa

drivers/clk/qcom/debugcc-sdm845.c

+0 −3
Original line number Diff line number Diff line
@@ -247,7 +247,6 @@ static const char *const debug_mux_parent_names[] = { 
	"gcc_sdcc1_apps_clk",

	"gcc_sdcc1_ice_core_clk",

	"gpu_cc_acd_cxo_clk",

	"gpu_cc_ahb_clk",

	"gpu_cc_crc_ahb_clk",

	"gpu_cc_cx_apb_clk",

	"gpu_cc_cx_gfx3d_clk",
@@ -720,8 +719,6 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x42, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 },

		{ "gpu_cc_acd_cxo_clk", 0x144, 4, GPU_CC,

			0x1F, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_ahb_clk", 0x144, 4, GPU_CC,

			0x11, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_crc_ahb_clk", 0x144, 4, GPU_CC,

			0x12, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_cx_apb_clk", 0x144, 4, GPU_CC,

drivers/clk/qcom/gpucc-sdm845.c

+0 −14
Original line number Diff line number Diff line
@@ -348,19 +348,6 @@ static struct clk_branch gpu_cc_acd_cxo_clk = { 
	},

};



static struct clk_branch gpu_cc_ahb_clk = {

	.halt_reg = 0x1078,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1078,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_crc_ahb_clk = {

	.halt_reg = 0x107c,

	.halt_check = BRANCH_HALT,
@@ -545,7 +532,6 @@ static struct clk_branch gpu_cc_pll_test_clk = { 
static struct clk_regmap *gpu_cc_sdm845_clocks[] = {

	[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,

	[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,

	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,

	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,

	[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,

	[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,

include/dt-bindings/clock/qcom,gpucc-sdm845.h

+26 −27
Original line number Diff line number Diff line
@@ -17,33 +17,32 @@ 
/* GPUCC clock registers */

#define GPU_CC_ACD_AHB_CLK					0

#define GPU_CC_ACD_CXO_CLK					1

#define GPU_CC_AHB_CLK						2

#define GPU_CC_CRC_AHB_CLK					3

#define GPU_CC_CX_APB_CLK					4

#define GPU_CC_CX_GMU_CLK					5

#define GPU_CC_CX_QDSS_AT_CLK					6

#define GPU_CC_CX_QDSS_TRIG_CLK					7

#define GPU_CC_CX_QDSS_TSCTR_CLK				8

#define GPU_CC_CX_SNOC_DVM_CLK					9

#define GPU_CC_CXO_AON_CLK					10

#define GPU_CC_CXO_CLK						11

#define GPU_CC_GX_GMU_CLK					12

#define GPU_CC_GX_QDSS_TSCTR_CLK				13

#define GPU_CC_GX_VSENSE_CLK					14

#define GPU_CC_PLL0_OUT_MAIN					15

#define GPU_CC_PLL0_OUT_ODD					16

#define GPU_CC_PLL0_OUT_TEST					17

#define GPU_CC_PLL1						18

#define GPU_CC_PLL1_OUT_EVEN					19

#define GPU_CC_PLL1_OUT_MAIN					20

#define GPU_CC_PLL1_OUT_ODD					21

#define GPU_CC_PLL1_OUT_TEST					22

#define GPU_CC_PLL_TEST_CLK					23

#define GPU_CC_SLEEP_CLK					24

#define GPU_CC_GMU_CLK_SRC					25

#define GPU_CC_CX_GFX3D_CLK					26

#define GPU_CC_CX_GFX3D_SLV_CLK					27

#define GPU_CC_PLL0						28

#define GPU_CC_CRC_AHB_CLK					2

#define GPU_CC_CX_APB_CLK					3

#define GPU_CC_CX_GMU_CLK					4

#define GPU_CC_CX_QDSS_AT_CLK					5

#define GPU_CC_CX_QDSS_TRIG_CLK					6

#define GPU_CC_CX_QDSS_TSCTR_CLK				7

#define GPU_CC_CX_SNOC_DVM_CLK					8

#define GPU_CC_CXO_AON_CLK					9

#define GPU_CC_CXO_CLK						10

#define GPU_CC_GX_GMU_CLK					11

#define GPU_CC_GX_QDSS_TSCTR_CLK				12

#define GPU_CC_GX_VSENSE_CLK					13

#define GPU_CC_PLL0_OUT_MAIN					14

#define GPU_CC_PLL0_OUT_ODD					15

#define GPU_CC_PLL0_OUT_TEST					16

#define GPU_CC_PLL1						17

#define GPU_CC_PLL1_OUT_EVEN					18

#define GPU_CC_PLL1_OUT_MAIN					19

#define GPU_CC_PLL1_OUT_ODD					20

#define GPU_CC_PLL1_OUT_TEST					21

#define GPU_CC_PLL_TEST_CLK					22

#define GPU_CC_SLEEP_CLK					23

#define GPU_CC_GMU_CLK_SRC					24

#define GPU_CC_CX_GFX3D_CLK					25

#define GPU_CC_CX_GFX3D_SLV_CLK					26

#define GPU_CC_PLL0						27



/* GPUCC reset clock registers */

#define GPUCC_GPU_CC_ACD_BCR					0