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Commit fa9160c1 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Add the GMU power perfcounters for A6XX"

parents fda5258f 4fc97e23

drivers/gpu/msm/a6xx_reg.h

+11 −0
Original line number Diff line number Diff line
@@ -798,8 +798,19 @@ 
#define A6XX_GMU_CM3_CFG			0x1F82D

#define A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE	0x1F840

#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0	0x1F841

#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1	0x1F842

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L	0x1F844

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H	0x1F845

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L	0x1F846

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H	0x1F847

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L	0x1F848

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H	0x1F849

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L	0x1F84A

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H	0x1F84B

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L	0x1F84C

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H	0x1F84D

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L	0x1F84E

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H	0x1F84F

#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL	0x1F8C0

#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST	0x1F8C1

#define A6XX_GMU_PWR_COL_SPTPRAC_HYST		0x1F8C2

drivers/gpu/msm/adreno.h

+1 −0
Original line number Diff line number Diff line
@@ -641,6 +641,7 @@ enum adreno_regs { 
	ADRENO_REG_GMU_HOST2GMU_INTR_SET,

	ADRENO_REG_GMU_HOST2GMU_INTR_CLR,

	ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO,

	ADRENO_REG_GPMU_POWER_COUNTER_ENABLE,

	ADRENO_REG_REGISTER_MAX,

};

drivers/gpu/msm/adreno_a5xx.c

+2 −0
Original line number Diff line number Diff line
@@ -3017,6 +3017,8 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A5XX_VBIF_XIN_HALT_CTRL1),

	ADRENO_REG_DEFINE(ADRENO_REG_VBIF_VERSION,

				A5XX_VBIF_VERSION),

	ADRENO_REG_DEFINE(ADRENO_REG_GPMU_POWER_COUNTER_ENABLE,

				A5XX_GPMU_POWER_COUNTER_ENABLE),

};



static const struct adreno_reg_offsets a5xx_reg_offsets = {

drivers/gpu/msm/adreno_a6xx.c

+36 −0
Original line number Diff line number Diff line
@@ -2431,12 +2431,47 @@ static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = { 
		A6XX_CP_ALWAYS_ON_COUNTER_HI, -1 },

};



static struct adreno_perfcount_register a6xx_pwrcounters_gpmu[] = {

	/*

	 * A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0 is used for the GPU

	 * busy count (see the PWR group above). Mark it as broken

	 * so it's not re-used.

	 */

	{ KGSL_PERFCOUNTER_BROKEN, 0, 0,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H, -1,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H, -1,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H, -1,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H, -1,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H, -1,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H, -1,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, },

};



#define A6XX_PERFCOUNTER_GROUP(offset, name) \

	ADRENO_PERFCOUNTER_GROUP(a6xx, offset, name)



#define A6XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags) \

	ADRENO_PERFCOUNTER_GROUP_FLAGS(a6xx, offset, name, flags)



#define A6XX_POWER_COUNTER_GROUP(offset, name) \

	ADRENO_POWER_COUNTER_GROUP(a6xx, offset, name)



static struct adreno_perfcount_group a6xx_perfcounter_groups

				[KGSL_PERFCOUNTER_GROUP_MAX] = {

	A6XX_PERFCOUNTER_GROUP(CP, cp),
@@ -2462,6 +2497,7 @@ static struct adreno_perfcount_group a6xx_perfcounter_groups 
		ADRENO_PERFCOUNTER_GROUP_FIXED),

	A6XX_PERFCOUNTER_GROUP_FLAGS(ALWAYSON, alwayson,

		ADRENO_PERFCOUNTER_GROUP_FIXED),

	A6XX_POWER_COUNTER_GROUP(GPMU, gpmu),

};



static struct adreno_perfcounters a6xx_perfcounters = {

drivers/gpu/msm/adreno_perfcounter.c

+6 −3
Original line number Diff line number Diff line
@@ -654,7 +654,7 @@ static void _power_counter_enable_gpmu(struct adreno_device *adreno_dev, 
{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_perfcount_register *reg;

	unsigned int shift = counter << 3;

	unsigned int shift = (counter << 3) % (sizeof(unsigned int) * 8);



	if (adreno_is_a530(adreno_dev)) {

		if (countable > 43)
@@ -662,13 +662,16 @@ static void _power_counter_enable_gpmu(struct adreno_device *adreno_dev, 
	} else if (adreno_is_a540(adreno_dev)) {

		if (countable > 47)

			return;

	} else if (adreno_is_a6xx(adreno_dev)) {

		if (countable > 34)

			return;

	} else

		/* return on platforms that have no GPMU */

		return;



	reg = &counters->groups[group].regs[counter];

	kgsl_regrmw(device, reg->select, 0xff << shift, countable << shift);

	kgsl_regwrite(device, A5XX_GPMU_POWER_COUNTER_ENABLE, 1);

	adreno_writereg(adreno_dev, ADRENO_REG_GPMU_POWER_COUNTER_ENABLE, 1);

	reg->value = 0;

}
@@ -684,7 +687,7 @@ static void _power_counter_enable_default(struct adreno_device *adreno_dev, 


	reg = &counters->groups[group].regs[counter];

	kgsl_regwrite(device, reg->select, countable);

	kgsl_regwrite(device, A5XX_GPMU_POWER_COUNTER_ENABLE, 1);

	adreno_writereg(adreno_dev, ADRENO_REG_GPMU_POWER_COUNTER_ENABLE, 1);

	reg->value = 0;

}