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Commit 4fc97e23 authored by Lynus Vaz's avatar Lynus Vaz
Browse files

msm: kgsl: Add the GMU power perfcounters for A6XX



Add the A6XX GMU power perfcounters so that they can be accessed.

Change-Id: I8185fd35c4b51596ddcf8e3a312564f30a7f245b
Signed-off-by: default avatarLynus Vaz <lvaz@codeaurora.org>
parent 76ecd06c
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+11 −0
Original line number Diff line number Diff line
@@ -798,8 +798,19 @@
#define A6XX_GMU_CM3_CFG			0x1F82D
#define A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE	0x1F840
#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0	0x1F841
#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1	0x1F842
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L	0x1F844
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H	0x1F845
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L	0x1F846
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H	0x1F847
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L	0x1F848
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H	0x1F849
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L	0x1F84A
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H	0x1F84B
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L	0x1F84C
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H	0x1F84D
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L	0x1F84E
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H	0x1F84F
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL	0x1F8C0
#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST	0x1F8C1
#define A6XX_GMU_PWR_COL_SPTPRAC_HYST		0x1F8C2
+36 −0
Original line number Diff line number Diff line
@@ -2431,12 +2431,47 @@ static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = {
		A6XX_CP_ALWAYS_ON_COUNTER_HI, -1 },
};

static struct adreno_perfcount_register a6xx_pwrcounters_gpmu[] = {
	/*
	 * A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0 is used for the GPU
	 * busy count (see the PWR group above). Mark it as broken
	 * so it's not re-used.
	 */
	{ KGSL_PERFCOUNTER_BROKEN, 0, 0,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H, -1,
		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, },
	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H, -1,
		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, },
	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H, -1,
		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, },
	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H, -1,
		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, },
	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H, -1,
		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, },
	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L,
		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H, -1,
		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, },
};

#define A6XX_PERFCOUNTER_GROUP(offset, name) \
	ADRENO_PERFCOUNTER_GROUP(a6xx, offset, name)

#define A6XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags) \
	ADRENO_PERFCOUNTER_GROUP_FLAGS(a6xx, offset, name, flags)

#define A6XX_POWER_COUNTER_GROUP(offset, name) \
	ADRENO_POWER_COUNTER_GROUP(a6xx, offset, name)

static struct adreno_perfcount_group a6xx_perfcounter_groups
				[KGSL_PERFCOUNTER_GROUP_MAX] = {
	A6XX_PERFCOUNTER_GROUP(CP, cp),
@@ -2462,6 +2497,7 @@ static struct adreno_perfcount_group a6xx_perfcounter_groups
		ADRENO_PERFCOUNTER_GROUP_FIXED),
	A6XX_PERFCOUNTER_GROUP_FLAGS(ALWAYSON, alwayson,
		ADRENO_PERFCOUNTER_GROUP_FIXED),
	A6XX_POWER_COUNTER_GROUP(GPMU, gpmu),
};

static struct adreno_perfcounters a6xx_perfcounters = {
+3 −0
Original line number Diff line number Diff line
@@ -662,6 +662,9 @@ static void _power_counter_enable_gpmu(struct adreno_device *adreno_dev,
	} else if (adreno_is_a540(adreno_dev)) {
		if (countable > 47)
			return;
	} else if (adreno_is_a6xx(adreno_dev)) {
		if (countable > 34)
			return;
	} else
		/* return on platforms that have no GPMU */
		return;