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Commit fa3aa59b authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
Browse files

msm: mdss: add support to program of HSTX drivers for DSI 12nm PHY 



Add support to program HSTX drivers in DSI 12nm PHY which is
needed for HS data transfer.

Change-Id: If3823f5a425f6d1c7781bd5d62d16d097f3b8ca0
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent 81d8dc52

drivers/video/fbdev/msm/mdss_dsi_phy.h

+14 −0
Original line number Diff line number Diff line
@@ -73,4 +73,18 @@ int mdss_dsi_12nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl); 
 */

int mdss_dsi_12nm_phy_shutdown(struct mdss_dsi_ctrl_pdata *ctrl);



/*

 * mdss_dsi_12nm_phy_hstx_drv_ctrl() - enable/disable HSTX drivers

 *

 * @ctrl: pointer to DSI controller structure

 * @enable: boolean to specify enable/disable the HSTX drivers

 *

 * Perform a sequence of register writes to enable/disable HSTX drivers.

 * This function assumes that the DSI bus clocks are turned on.

 */



void mdss_dsi_12nm_phy_hstx_drv_ctrl(

	struct mdss_dsi_ctrl_pdata *ctrl, bool enable);





#endif /* MDSS_DSI_PHY_H */

drivers/video/fbdev/msm/mdss_dsi_phy_12nm.c

+20 −0
Original line number Diff line number Diff line
@@ -16,8 +16,11 @@ 


#define T_TA_GO_TIM_COUNT                    0x014

#define T_TA_SURE_TIM_COUNT                  0x018

#define HSTX_DRIV_INDATA_CTRL_CLKLANE        0x0c0

#define HSTX_DATAREV_CTRL_CLKLANE            0x0d4

#define HSTX_DRIV_INDATA_CTRL_LANE0          0x100

#define HSTX_READY_DLY_DATA_REV_CTRL_LANE0   0x114

#define HSTX_DRIV_INDATA_CTRL_LANE1          0x140

#define HSTX_READY_DLY_DATA_REV_CTRL_LANE1   0x154

#define HSTX_CLKLANE_REQSTATE_TIM_CTRL       0x180

#define HSTX_CLKLANE_HS0STATE_TIM_CTRL       0x188
@@ -27,8 +30,10 @@ 
#define HSTX_DATALANE_HS0STATE_TIM_CTRL      0x1c8

#define HSTX_DATALANE_TRAILSTATE_TIM_CTRL    0x1cc

#define HSTX_DATALANE_EXITSTATE_TIM_CTRL     0x1d0

#define HSTX_DRIV_INDATA_CTRL_LANE2          0x200

#define HSTX_READY_DLY_DATA_REV_CTRL_LANE2   0x214

#define HSTX_READY_DLY_DATA_REV_CTRL_LANE3   0x254

#define HSTX_DRIV_INDATA_CTRL_LANE3          0x240

#define CTRL0                                0x3e8

#define SYS_CTRL                             0x3f0

#define REQ_DLY                              0x3fc
@@ -102,3 +107,18 @@ int mdss_dsi_12nm_phy_shutdown(struct mdss_dsi_ctrl_pdata *ctrl) 
	return 0;

}



void mdss_dsi_12nm_phy_hstx_drv_ctrl(

	struct mdss_dsi_ctrl_pdata *ctrl, bool enable)

{

	u32 data = 0;



	if (enable)

		data = BIT(2) | BIT(3);



	DSI_PHY_W32(ctrl->phy_io.base, HSTX_DRIV_INDATA_CTRL_CLKLANE, data);

	DSI_PHY_W32(ctrl->phy_io.base, HSTX_DRIV_INDATA_CTRL_LANE0, data);

	DSI_PHY_W32(ctrl->phy_io.base, HSTX_DRIV_INDATA_CTRL_LANE1, data);

	DSI_PHY_W32(ctrl->phy_io.base, HSTX_DRIV_INDATA_CTRL_LANE2, data);

	DSI_PHY_W32(ctrl->phy_io.base, HSTX_DRIV_INDATA_CTRL_LANE3, data);

	wmb(); /* make sure DSI PHY registers are programmed */

}

drivers/video/fbdev/msm/msm_mdss_io_8974.c

+15 −0
Original line number Diff line number Diff line
@@ -1280,6 +1280,13 @@ void mdss_dsi_phy_init(struct mdss_dsi_ctrl_pdata *ctrl) 
	}

}



static void mdss_dsi_phy_hstx_drv_ctrl(

	struct mdss_dsi_ctrl_pdata *ctrl, bool enable)

{

	if (ctrl->shared_data->phy_rev == DSI_PHY_REV_12NM)

		mdss_dsi_12nm_phy_hstx_drv_ctrl(ctrl, enable);

}



void mdss_dsi_core_clk_deinit(struct device *dev, struct dsi_shared_data *sdata)

{

	if (sdata->mmss_misc_ahb_clk)
@@ -2186,6 +2193,12 @@ int mdss_dsi_pre_clkoff_cb(void *priv, 


	pdata = &ctrl->panel_data;



	if ((clk & MDSS_DSI_LINK_CLK) && (l_type == MDSS_DSI_LINK_HS_CLK) &&

		(new_state == MDSS_DSI_CLK_OFF)) {

		/* Disable HS TX driver in DSI PHY if applicable */

		mdss_dsi_phy_hstx_drv_ctrl(ctrl, false);

	}



	if ((clk & MDSS_DSI_LINK_CLK) && (l_type == MDSS_DSI_LINK_LP_CLK) &&

		(new_state == MDSS_DSI_CLK_OFF)) {

		/*
@@ -2298,6 +2311,8 @@ int mdss_dsi_post_clkon_cb(void *priv, 
				goto error;

			}

		}

		/* Enable HS TX driver in DSI PHY if applicable */

		mdss_dsi_phy_hstx_drv_ctrl(ctrl, true);

	}

error:

	return rc;