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Commit 81d8dc52 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
Browse files

msm: mdss: add support for DSI 12nm PHY in DSI driver 



Add support for DSI 12nm PHY programming in the DSI driver as per
the recommended DSI PHY programming sequence.

Change-Id: Ic2c6eed0147903970da85781818d8ccd94c40021
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent b0008fd8

Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt

+4 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ Required properties: 
					timing settings for the panel.

- qcom,mdss-dsi-panel-timings-phy-v2:	An array of length 40 char that specifies the PHY version 2

					lane timing settings for the panel.

- qcom,mdss-dsi-panel-timings-phy-12nm: An array of length 8 char that specifies the 12nm DSI PHY

					lane timing settings for the panel.

- qcom,mdss-dsi-on-command:		A byte stream formed by multiple dcs packets base on

					qcom dsi controller protocol.

					byte 0: dcs data type
@@ -631,6 +633,8 @@ Example: 
                                23 20 06 09 05 03 04 a0

                                23 20 06 09 05 03 04 a0

                                23 2e 06 08 05 03 04 a0];

                qcom,mdss-dsi-panel-timings-phy-12nm =

				[a9 4e 56 0b 8a 4d 0b d6];

		qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00

					29 01 00 00 10 00 02 FF 99];

		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

drivers/video/fbdev/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ mdss-dsi-objs := mdss_dsi.o mdss_dsi_host.o mdss_dsi_cmd.o mdss_dsi_status.o 
mdss-dsi-objs += mdss_dsi_panel.o

mdss-dsi-objs += msm_mdss_io_8974.o

mdss-dsi-objs += mdss_dsi_phy.o

mdss-dsi-objs += mdss_dsi_phy_12nm.o

mdss-dsi-objs += mdss_dsi_clk.o

obj-$(CONFIG_FB_MSM_MDSS) += mdss-dsi.o

obj-$(CONFIG_FB_MSM_MDSS) += mdss_panel.o

drivers/video/fbdev/msm/mdss_dsi.c

+12 −15
Original line number Diff line number Diff line
@@ -3976,12 +3976,11 @@ static int mdss_dsi_parse_ctrl_params(struct platform_device *ctrl_pdev, 
	if (!data) {

		pr_err("%s:%d, Unable to read Phy Strength ctrl settings\n",

			__func__, __LINE__);

		return -EINVAL;

	}



	} else {

		pinfo->mipi.dsi_phy_db.strength_len = len;

		for (i = 0; i < len; i++)

			pinfo->mipi.dsi_phy_db.strength[i] = data[i];

	}



	pinfo->mipi.dsi_phy_db.reg_ldo_mode = of_property_read_bool(

		ctrl_pdev->dev.of_node, "qcom,regulator-ldo-mode");
@@ -3991,12 +3990,11 @@ static int mdss_dsi_parse_ctrl_params(struct platform_device *ctrl_pdev, 
	if (!data) {

		pr_err("%s:%d, Unable to read Phy regulator settings\n",

			__func__, __LINE__);

		return -EINVAL;

	}



	} else {

		pinfo->mipi.dsi_phy_db.regulator_len = len;

		for (i = 0; i < len; i++)

			pinfo->mipi.dsi_phy_db.regulator[i] = data[i];

	}



	data = of_get_property(ctrl_pdev->dev.of_node,

		"qcom,platform-bist-ctrl", &len);
@@ -4012,12 +4010,11 @@ static int mdss_dsi_parse_ctrl_params(struct platform_device *ctrl_pdev, 
	if (!data) {

		pr_err("%s:%d, Unable to read Phy lane configure settings\n",

			__func__, __LINE__);

		return -EINVAL;

	}



	} else {

		pinfo->mipi.dsi_phy_db.lanecfg_len = len;

		for (i = 0; i < len; i++)

			pinfo->mipi.dsi_phy_db.lanecfg[i] = data[i];

	}



	ctrl_pdata->timing_db_mode = of_property_read_bool(

		ctrl_pdev->dev.of_node, "qcom,timing-db-mode");

drivers/video/fbdev/msm/mdss_dsi.h

+1 −0
Original line number Diff line number Diff line
@@ -337,6 +337,7 @@ struct dsi_panel_timing { 
	struct mdss_panel_timing timing;

	uint32_t phy_timing[12];

	uint32_t phy_timing_8996[40];

	uint32_t phy_timing_12nm[8];

	/* DSI_CLKOUT_TIMING_CTRL */

	char t_clk_post;

	char t_clk_pre;

drivers/video/fbdev/msm/mdss_dsi_host.c

+18 −0
Original line number Diff line number Diff line
@@ -303,6 +303,20 @@ void mdss_dsi_read_phy_revision(struct mdss_dsi_ctrl_pdata *ctrl) 
		 */

		reg_val = MIPI_INP(ctrl->phy_io.base + 0x20c);

		reg_val = reg_val >> 4;

		if (!reg_val) {

			/*

			 * DSI_0_PHY_DSIPHY_REVISION_ID3 for 12nm PHY

			 * reset value = 0x20

			 * 7:4 Major

			 * 3:0 Minor

			 */

			reg_val = MIPI_INP(ctrl->phy_io.base + 0x3dc);

			reg_val = reg_val >> 4;

			if (reg_val == 0x2) {

				ctrl->shared_data->phy_rev = DSI_PHY_REV_12NM;

				return;

			}

		}

	}



	if (reg_val == DSI_PHY_REV_20)
@@ -413,6 +427,9 @@ void mdss_dsi_host_init(struct mdss_panel_data *pdata) 
	/* DSI_LAN_SWAP_CTRL */

	MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x00b0, ctrl_pdata->dlane_swap);



	if (ctrl_pdata->shared_data->phy_rev == DSI_PHY_REV_12NM)

		goto next;



	/* clock out ctrl */

	data = pinfo->t_clk_post & 0x3f;	/* 6 bits */

	data <<= 8;
@@ -420,6 +437,7 @@ void mdss_dsi_host_init(struct mdss_panel_data *pdata) 
	/* DSI_CLKOUT_TIMING_CTRL */

	MIPI_OUTP((ctrl_pdata->ctrl_base) + 0xc4, data);



next:

	data = 0;

	if (pinfo->rx_eot_ignore)

		data |= BIT(4);