Merge branch 'topic/xilinx' into for-linus

as two channels, one is to transmit to the video device and another is

to receive from the video device.

Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream

target devices. It can be configured to have one channel or two channels.

If configured as two channels, one is to transmit to the device and another

is to receive from the device.

Xilinx AXI CDMA engine, it does transfers between memory-mapped source

address and a memory-mapped destination address.

Required properties:

- compatible: Should be "xlnx,axi-vdma-1.00.a"

- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or

	      "xlnx,axi-cdma-1.00.a""

- #dma-cells: Should be <1>, see "dmas" property below

- reg: Should contain VDMA registers location and length.

- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.

- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).

- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.

- dma-channel child node: Should have at least one channel and can have up to

	two channels per device. This node specifies the properties of each

	DMA channel (see child node properties below).

- clocks: Input clock specifier. Refer to common clock bindings.

- clock-names: List of input clocks

	For VDMA:

	Required elements: "s_axi_lite_aclk"

	Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",

			   "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"

	For CDMA:

	Required elements: "s_axi_lite_aclk", "m_axi_aclk"

	FOR AXIDMA:

	Required elements: "s_axi_lite_aclk"

	Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",

			   "m_axi_sg_aclk"

Required properties for VDMA:

- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.

Optional properties:

- xlnx,include-sg: Tells configured for Scatter-mode in

	the hardware.

Optional properties for VDMA:

- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.

	It takes following values:

	{1}, flush both channels

Optional child node properties:

- xlnx,include-dre: Tells hardware is configured for Data

	Realignment Engine.

Optional child node properties for VDMA:

- xlnx,genlock-mode: Tells Genlock synchronization is

	enabled/disabled in hardware.

	compatible = "xlnx,axi-vdma-1.00.a";

	#dma_cells = <1>;

	reg = < 0x40030000 0x10000 >;

	dma-ranges = <0x00000000 0x00000000 0x40000000>;

	xlnx,num-fstores = <0x8>;

	xlnx,flush-fsync = <0x1>;

	xlnx,addrwidth = <0x20>;

	clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;

	clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",

		      "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";

	dma-channel@40030000 {

		compatible = "xlnx,axi-vdma-mm2s-channel";

		interrupts = < 0 54 4 >;

config XILINX_VDMA

	tristate "Xilinx AXI VDMA Engine"

	depends on (ARCH_ZYNQ || MICROBLAZE)

	depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)

	select DMA_ENGINE

	help

	  Enable support for Xilinx AXI VDMA Soft IP.

	int ext_fsync;

};

/**

 * enum xdma_ip_type: DMA IP type.

 *

 * XDMA_TYPE_AXIDMA: Axi dma ip.

 * XDMA_TYPE_CDMA: Axi cdma ip.

 * XDMA_TYPE_VDMA: Axi vdma ip.

 *

 */

enum xdma_ip_type {

	XDMA_TYPE_AXIDMA = 0,

	XDMA_TYPE_CDMA,

	XDMA_TYPE_VDMA,

};

int xilinx_vdma_channel_set_config(struct dma_chan *dchan,

					struct xilinx_vdma_config *cfg);