Merge branch 'topic/tegra' into for-linus

* NVIDIA Tegra Audio DMA (ADMA) controller

The Tegra Audio DMA controller that is used for transferring data

between system memory and the Audio Processing Engine (APE).

Required properties:

- compatible: Must be "nvidia,tegra210-adma".

- reg: Should contain DMA registers location and length. This should be

  a single entry that includes all of the per-channel registers in one

  contiguous bank.

- interrupt-parent: Phandle to the interrupt parent controller.

- interrupts: Should contain all of the per-channel DMA interrupts in

  ascending order with respect to the DMA channel index.

- clocks: Must contain one entry for the ADMA module clock

  (TEGRA210_CLK_D_AUDIO).

- clock-names: Must contain the name "d_audio" for the corresponding

  'clocks' entry.

- #dma-cells : Must be 1. The first cell denotes the receive/transmit

  request number and should be between 1 and the maximum number of

  requests supported. This value corresponds to the RX/TX_REQUEST_SELECT

  fields in the ADMA_CHn_CTRL register.

Example:

adma: dma@702e2000 {

	compatible = "nvidia,tegra210-adma";

	reg = <0x0 0x702e2000 0x0 0x2000>;

	interrupt-parent = <&tegra_agic>;

	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;

	clock-names = "d_audio";

	#dma-cells = <1>;

};

S:	Supported

F:	drivers/clk/tegra/

TEGRA DMA DRIVER

TEGRA DMA DRIVERS

M:	Laxman Dewangan <ldewangan@nvidia.com>

M:	Jon Hunter <jonathanh@nvidia.com>

S:	Supported

F:	drivers/dma/tegra20-apb-dma.c

F:	drivers/dma/tegra*

TEGRA I2C DRIVER

M:	Laxman Dewangan <ldewangan@nvidia.com>

	  This DMA controller transfers data from memory to peripheral fifo

	  or vice versa. It does not support memory to memory data transfer.

config TEGRA210_ADMA

	bool "NVIDIA Tegra210 ADMA support"

	depends on ARCH_TEGRA_210_SOC

	select DMA_ENGINE

	select DMA_VIRTUAL_CHANNELS

	select PM_CLK

	help

	  Support for the NVIDIA Tegra210 ADMA controller driver. The

	  DMA controller has multiple DMA channels and is used to service

	  various audio clients in the Tegra210 audio processing engine

	  (APE). This DMA controller transfers data from memory to

	  peripheral and vice versa. It does not support memory to

	  memory data transfer.

config TIMB_DMA

	tristate "Timberdale FPGA DMA support"

	depends on MFD_TIMBERDALE

obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o

obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o

obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o

obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o

obj-$(CONFIG_TIMB_DMA) += timb_dma.o

obj-$(CONFIG_TI_CPPI41) += cppi41.o

obj-$(CONFIG_TI_DMA_CROSSBAR) += ti-dma-crossbar.o

#define TEGRA_APBDMA_CSR_ONCE			BIT(27)

#define TEGRA_APBDMA_CSR_FLOW			BIT(21)

#define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT		16

#define TEGRA_APBDMA_CSR_REQ_SEL_MASK		0x1F

#define TEGRA_APBDMA_CSR_WCOUNT_MASK		0xFFFC

/* STATUS register */

/* Channel base address offset from APBDMA base address */

#define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET	0x1000

#define TEGRA_APBDMA_SLAVE_ID_INVALID	(TEGRA_APBDMA_CSR_REQ_SEL_MASK + 1)

struct tegra_dma;

/*

	}

	memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));

	if (!tdc->slave_id)

	if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID) {

		if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)

			return -EINVAL;

		tdc->slave_id = sconfig->slave_id;

	}

	tdc->config_init = true;

	return 0;

}

	}

	pm_runtime_put(tdma->dev);

	tdc->slave_id = 0;

	tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;

}

static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,

	struct dma_chan *chan;

	struct tegra_dma_channel *tdc;

	if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) {

		dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);

		return NULL;

	}

	chan = dma_get_any_slave_channel(&tdma->dma_dev);

	if (!chan)

		return NULL;

				&tdma->dma_dev.channels);

		tdc->tdma = tdma;

		tdc->id = i;

		tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;

		tasklet_init(&tdc->tasklet, tegra_dma_tasklet,

				(unsigned long)tdc);