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Commit f746929f authored by Russell King's avatar Russell King
Browse files

Revert "ARM: OMAP4: remove dead kconfig option OMAP4_ERRATA_I688" 



This reverts commit 606da482.

We actually need this code for proper behaviour of OMAP4, and it needs
fixing a different way other than just removing the code.  Disabling
code which is necessary in the hopes of persuing multiplatform kernels
is a stupid approach.

Acked-by: default avatarTony Lindgren <tony@atomide.com>
Acked-by: default avatarRichard Woodruff <r-woodruff2@ti.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 4e1f8a6f

arch/arm/mach-omap2/Kconfig

+21 −0
Original line number Diff line number Diff line
@@ -240,6 +240,27 @@ config OMAP3_SDRC_AC_TIMING 
	  wish to say no.  Selecting yes without understanding what is

	  going on could result in system crashes;



config OMAP4_ERRATA_I688

	bool "OMAP4 errata: Async Bridge Corruption"

	depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM

	select ARCH_HAS_BARRIERS

	help

	  If a data is stalled inside asynchronous bridge because of back

	  pressure, it may be accepted multiple times, creating pointer

	  misalignment that will corrupt next transfers on that data path

	  until next reset of the system (No recovery procedure once the

	  issue is hit, the path remains consistently broken). Async bridge

	  can be found on path between MPU to EMIF and MPU to L3 interconnect.

	  This situation can happen only when the idle is initiated by a

	  Master Request Disconnection (which is trigged by software when

	  executing WFI on CPU).

	  The work-around for this errata needs all the initiators connected

	  through async bridge must ensure that data path is properly drained

	  before issuing WFI. This condition will be met if one Strongly ordered

	  access is performed to the target right before executing the WFI.

	  In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.

	  IO barrier ensure that there is no synchronisation loss on initiators

	  operating on both interconnect port simultaneously.

endmenu



endif

arch/arm/mach-omap2/common.c

+1 −0
Original line number Diff line number Diff line
@@ -30,4 +30,5 @@ int __weak omap_secure_ram_reserve_memblock(void) 
void __init omap_reserve(void)

{

	omap_secure_ram_reserve_memblock();

	omap_barrier_reserve_memblock();

}

arch/arm/mach-omap2/common.h

+3 −0
Original line number Diff line number Diff line
@@ -200,6 +200,9 @@ void __init omap4_map_io(void); 
void __init omap5_map_io(void);

void __init ti81xx_map_io(void);



/* omap_barriers_init() is OMAP4 only */

void omap_barriers_init(void);



/**

 * omap_test_timeout - busy-loop, testing a condition

 * @cond: condition to test until it evaluates to true

arch/arm/mach-omap2/io.c

+2 −0
Original line number Diff line number Diff line
@@ -306,6 +306,7 @@ void __init am33xx_map_io(void) 
void __init omap4_map_io(void)

{

	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));

	omap_barriers_init();

}

#endif
@@ -313,6 +314,7 @@ void __init omap4_map_io(void) 
void __init omap5_map_io(void)

{

	iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));

	omap_barriers_init();

}

#endif

/*

arch/arm/mach-omap2/omap-secure.h

+7 −0
Original line number Diff line number Diff line
@@ -70,6 +70,13 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, 
extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);

extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);



#ifdef CONFIG_OMAP4_ERRATA_I688

extern int omap_barrier_reserve_memblock(void);

#else

static inline void omap_barrier_reserve_memblock(void)

{ }

#endif



#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER

void set_cntfreq(void);

#else