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Commit 4e1f8a6f authored by Russell King's avatar Russell King
Browse files

ARM: add soc memory barrier extension 



Add an extension to the heavy barrier code to allow a SoC specific
memory barrier function to be provided.  This is needed for platforms
where the interconnect has weak ordering, and thus needs assistance
to ensure that memory writes are properly visible in the correct order
to other parts of the system.

Acked-by: default avatarTony Lindgren <tony@atomide.com>
Acked-by: default avatarRichard Woodruff <r-woodruff2@ti.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent f8130906

arch/arm/include/asm/barrier.h

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#endif



#ifdef CONFIG_ARM_HEAVY_MB

extern void (*soc_mb)(void);

extern void arm_heavy_mb(void);

#define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0)

#else

arch/arm/mm/flush.c

+4 −0
Original line number Diff line number Diff line
@@ -22,12 +22,16 @@ 
#include "mm.h"



#ifdef CONFIG_ARM_HEAVY_MB

void (*soc_mb)(void);



void arm_heavy_mb(void)

{

#ifdef CONFIG_OUTER_CACHE_SYNC

	if (outer_cache.sync)

		outer_cache.sync();

#endif

	if (soc_mb)

		soc_mb();

}

EXPORT_SYMBOL(arm_heavy_mb);

#endif