Merge "ARM: dts: msm: add smmu device support for msm8917"

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

&soc {

	gfx_iommu: qcom,iommu@1f00000 {

		status = "ok";

		compatible = "qcom,qsmmu-v500";

		reg = <0x1f00000 0x10000>,

			<0x1ee2000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <1>;

		qcom,tz-device-id = "GPU";

		qcom,skip-init;

		qcom,enable-static-cb;

		qcom,dynamic;

		qcom,use-3-lvl-tables;

		#global-interrupts = <0>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clock_gcc clk_gcc_smmu_cfg_clk>,

				<&clock_gcc clk_gcc_gfx_tcu_clk>;

		clock-names = "iface_clk", "core_clk";

	};

	apps_iommu: qcom,iommu@1e00000 {

		status = "okay";

		compatible = "qcom,qsmmu-v500";

		reg = <0x1e00000 0x40000>,

			<0x1ee2000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,tz-device-id = "APPS";

		qcom,skip-init;

		qcom,disable-atos;

		ranges;

		qcom,enable-static-cb;

		qcom,use-3-lvl-tables;

		#global-interrupts = <0>;

		#size-cells = <1>;

		#address-cells = <1>;

		interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clock_gcc clk_gcc_smmu_cfg_clk>,

				<&clock_gcc clk_gcc_apss_tcu_clk>;

		clock-names = "iface_clk", "core_clk";

	};

};

#include "msm8917-bus.dtsi"

#include "msm8917-mdss.dtsi"

#include "msm8917-mdss-pll.dtsi"

#include "msm-arm-smmu-8917.dtsi"

&soc {

	#address-cells = <1>;