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Commit e9daa0ea authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-3.9-soc-t114' of... 

Merge tag 'tegra-for-3.9-soc-t114' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc

From Stepen Warren:
ARM: tegra: add Tegra114 SoC support

This pull request adds initial support for the Tegra114 SoC, which
integrates a quad-core ARM Cortex-A15 CPU. I'm proud to observe that we
posted the initial versions of these patches before the final official
announcement of this chip.

These patches are enough to boot with a UART-based console, support the
Dalmore and Pluto reference/evaluation boards, instantiate the GPIO and
pinctrl drivers, and enable a cpuidle state. As yet, no clocks or
storage devices are supported, but patches for those will follow shortly.

This pull request is based on (most of) the previous pull request with
tag tegra-for-3.9-soc-cpuidle, followed by a merge of the previous pull
request with tag tegra-for-3.9-scu-base-rework.

* tag 'tegra-for-3.9-soc-t114' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra

: (24 commits)
  ARM: DT: tegra114: add pinmux DT entry
  ARM: DT: tegra114: add GPIO DT entry
  ARM: tegra114: select PINCTRL for Tegra114 SoC
  ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE support
  ARM: tegra: Add SMMU entry to Tegra114 DT
  ARM: tegra: add AHB entry to Tegra114 DT
  ARM: tegra: Add initial support for Tegra114 SoC.
  ARM: dt: tegra114: Add new board, Pluto
  ARM: dt: tegra114: Add new board, Dalmore
  ARM: dt: tegra114: Add new SoC base, Tegra114 SoC
  ARM: tegra: fuse: Add chip ID Tegra114 0x35
  ARM: OMAP: Make use of available scu_a9_get_base() interface
  ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9
  ARM: Add API to detect SCU base address from CP15
  ARM: tegra: Use DT /cpu node to detect number of CPU core
  ARM: tegra: Add CPU nodes to Tegra30 device tree
  ARM: tegra: Add CPU nodes to Tegra20 device tree
  ARM: perf: simplify __hw_perf_event_init err handling
  ARM: perf: remove unnecessary checks for idx < 0
  ARM: perf: handle armpmu_register failing
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>

Remove/add conflict in arch/arm/mach-tegra/common.c resolved.
Remove/remove conflict in arch/arm/mach-tegra/platsmp.c. Leave the empty
stub function for now since removing it in the merge commit is confusing;
will be cleaned up in a separate commit.  # # It looks like you may be
committing a merge.  # If this is not correct, please remove the file #
.git/MERGE_HEAD # and try again.
parents c8bfea36 031b77af

arch/arm/boot/dts/Makefile

+3 −1
Original line number Original line Diff line number Diff line
@@ -144,7 +144,9 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 
	tegra20-ventana.dtb \

	tegra20-ventana.dtb \

	tegra20-whistler.dtb \

	tegra20-whistler.dtb \

	tegra30-cardhu-a02.dtb \

	tegra30-cardhu-a02.dtb \

	tegra30-cardhu-a04.dtb

	tegra30-cardhu-a04.dtb \

	tegra114-dalmore.dtb \

	tegra114-pluto.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \

dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \

	vexpress-v2p-ca9.dtb \

	vexpress-v2p-ca9.dtb \

	vexpress-v2p-ca15-tc1.dtb \

	vexpress-v2p-ca15-tc1.dtb \

arch/arm/boot/dts/tegra114-dalmore.dts

0 → 100644
+21 −0
Original line number Original line Diff line number Diff line 
/dts-v1/;



/include/ "tegra114.dtsi"



/ {

	model = "NVIDIA Tegra114 Dalmore evaluation board";

	compatible = "nvidia,dalmore", "nvidia,tegra114";



	memory {

		reg = <0x80000000 0x40000000>;

	};



	serial@70006300 {

		status = "okay";

		clock-frequency = <408000000>;

	};



	pmc {

		nvidia,invert-interrupt;

	};

};

arch/arm/boot/dts/tegra114-pluto.dts

0 → 100644
+21 −0
Original line number Original line Diff line number Diff line 
/dts-v1/;



/include/ "tegra114.dtsi"



/ {

	model = "NVIDIA Tegra114 Pluto evaluation board";

	compatible = "nvidia,pluto", "nvidia,tegra114";



	memory {

		reg = <0x80000000 0x40000000>;

	};



	serial@70006300 {

		status = "okay";

		clock-frequency = <408000000>;

	};



	pmc {

		nvidia,invert-interrupt;

	};

};

arch/arm/boot/dts/tegra114.dtsi

0 → 100644
+153 −0
Original line number Original line Diff line number Diff line 
/include/ "skeleton.dtsi"



/ {

	compatible = "nvidia,tegra114";

	interrupt-parent = <&gic>;



	gic: interrupt-controller {

		compatible = "arm,cortex-a15-gic";

		#interrupt-cells = <3>;

		interrupt-controller;

		reg = <0x50041000 0x1000>,

		      <0x50042000 0x1000>,

		      <0x50044000 0x2000>,

		      <0x50046000 0x2000>;

		interrupts = <1 9 0xf04>;

	};



	timer@60005000 {

		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";

		reg = <0x60005000 0x400>;

		interrupts = <0 0 0x04

			      0 1 0x04

			      0 41 0x04

			      0 42 0x04

			      0 121 0x04

			      0 122 0x04>;

	};



	tegra_car: clock {

		compatible = "nvidia,tegra114-car, nvidia,tegra30-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

	};



	ahb: ahb {

		compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";

		reg = <0x6000c004 0x14c>;

	};



	gpio: gpio {

		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";

		reg = <0x6000d000 0x1000>;

		interrupts = <0 32 0x04

			      0 33 0x04

			      0 34 0x04

			      0 35 0x04

			      0 55 0x04

			      0 87 0x04

			      0 89 0x04

			      0 125 0x04>;

		#gpio-cells = <2>;

		gpio-controller;

		#interrupt-cells = <2>;

		interrupt-controller;

	};



	pinmux: pinmux {

		compatible = "nvidia,tegra114-pinmux";

		reg = <0x70000868 0x148		/* Pad control registers */

		       0x70003000 0x40c>;	/* Mux registers */

	};



	serial@70006000 {

		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";

		reg = <0x70006000 0x40>;

		reg-shift = <2>;

		interrupts = <0 36 0x04>;

		status = "disabled";

	};



	serial@70006040 {

		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";

		reg = <0x70006040 0x40>;

		reg-shift = <2>;

		interrupts = <0 37 0x04>;

		status = "disabled";

	};



	serial@70006200 {

		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";

		reg = <0x70006200 0x100>;

		reg-shift = <2>;

		interrupts = <0 46 0x04>;

		status = "disabled";

	};



	serial@70006300 {

		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";

		reg = <0x70006300 0x100>;

		reg-shift = <2>;

		interrupts = <0 90 0x04>;

		status = "disabled";

	};



	rtc {

		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";

		reg = <0x7000e000 0x100>;

		interrupts = <0 2 0x04>;

	};



	pmc {

		compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";

		reg = <0x7000e400 0x400>;

	};



	iommu {

		compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";

		reg = <0x7000f010 0x02c

		       0x7000f1f0 0x010

		       0x7000f228 0x074>;

		nvidia,#asids = <4>;

		dma-window = <0 0x40000000>;

		nvidia,swgroups = <0x18659fe>;

		nvidia,ahb = <&ahb>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <1>;

		};



		cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <2>;

		};



		cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <3>;

		};

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <1 13 0xf08>,

			     <1 14 0xf08>,

			     <1 11 0xf08>,

			     <1 10 0xf08>;

	};

};

arch/arm/boot/dts/tegra20.dtsi

+17 −0
Original line number Original line Diff line number Diff line
@@ -489,6 +489,23 @@ 
		status = "disabled";

		status = "disabled";

	};

	};





	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

		};

	};



	pmu {

	pmu {

		compatible = "arm,cortex-a9-pmu";

		compatible = "arm,cortex-a9-pmu";

		interrupts = <0 56 0x04

		interrupts = <0 56 0x04