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Commit c8bfea36 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-3.9-soc-cpuidle' of... 

Merge tag 'tegra-for-3.9-soc-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc

From Stephen Warren:
ARM: tegra: cpuidle enhancements

This pull request implements a new "LP2" cpuidle state for Tegra20,
which makes use of the couple cpuidle feature.

It is based on (most of) the previous pull request, with tag
tegra-for-3.9-soc-usb.

* tag 'tegra-for-3.9-soc-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra

:
  ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
  ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit
  clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops
  ARM: tegra20: cpuidle: add powered-down state for secondary CPU
  ARM: tegra: add pending SGI checking API

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ceca718f 1d328606

arch/arm/mach-tegra/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ comment "NVIDIA Tegra options" 


config ARCH_TEGRA_2x_SOC

	bool "Enable support for Tegra20 family"

	select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP

	select ARCH_REQUIRE_GPIOLIB

	select ARM_ERRATA_720789

	select ARM_ERRATA_742230 if SMP

arch/arm/mach-tegra/cpuidle-tegra20.c

+193 −4
Original line number Diff line number Diff line
@@ -22,21 +22,199 @@ 
#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/cpuidle.h>

#include <linux/cpu_pm.h>

#include <linux/clockchips.h>

#include <linux/clk/tegra.h>



#include <asm/cpuidle.h>

#include <asm/proc-fns.h>

#include <asm/suspend.h>

#include <asm/smp_plat.h>



#include "pm.h"

#include "sleep.h"

#include "iomap.h"

#include "irq.h"

#include "flowctrl.h"



#ifdef CONFIG_PM_SLEEP

static bool abort_flag;

static atomic_t abort_barrier;

static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,

				    struct cpuidle_driver *drv,

				    int index);

#endif



static struct cpuidle_state tegra_idle_states[] = {

	[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),

#ifdef CONFIG_PM_SLEEP

	[1] = {

		.enter			= tegra20_idle_lp2_coupled,

		.exit_latency		= 5000,

		.target_residency	= 10000,

		.power_usage		= 0,

		.flags			= CPUIDLE_FLAG_TIME_VALID |

					  CPUIDLE_FLAG_COUPLED,

		.name			= "powered-down",

		.desc			= "CPU power gated",

	},

#endif

};



static struct cpuidle_driver tegra_idle_driver = {

	.name = "tegra_idle",

	.owner = THIS_MODULE,

	.en_core_tk_irqen = 1,

	.state_count = 1,

	.states = {

		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),

	},

};



static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);



#ifdef CONFIG_PM_SLEEP

#ifdef CONFIG_SMP

static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);



static int tegra20_reset_sleeping_cpu_1(void)

{

	int ret = 0;



	tegra_pen_lock();



	if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)

		tegra20_cpu_shutdown(1);

	else

		ret = -EINVAL;



	tegra_pen_unlock();



	return ret;

}



static void tegra20_wake_cpu1_from_reset(void)

{

	tegra_pen_lock();



	tegra20_cpu_clear_resettable();



	/* enable cpu clock on cpu */

	tegra_enable_cpu_clock(1);



	/* take the CPU out of reset */

	tegra_cpu_out_of_reset(1);



	/* unhalt the cpu */

	flowctrl_write_cpu_halt(1, 0);



	tegra_pen_unlock();

}



static int tegra20_reset_cpu_1(void)

{

	if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())

		return 0;



	tegra20_wake_cpu1_from_reset();

	return -EBUSY;

}

#else

static inline void tegra20_wake_cpu1_from_reset(void)

{

}



static inline int tegra20_reset_cpu_1(void)

{

	return 0;

}

#endif



static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,

					   struct cpuidle_driver *drv,

					   int index)

{

	struct cpuidle_state *state = &drv->states[index];

	u32 cpu_on_time = state->exit_latency;

	u32 cpu_off_time = state->target_residency - state->exit_latency;



	while (tegra20_cpu_is_resettable_soon())

		cpu_relax();



	if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())

		return false;



	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);



	tegra_idle_lp2_last(cpu_on_time, cpu_off_time);



	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);



	if (cpu_online(1))

		tegra20_wake_cpu1_from_reset();



	return true;

}



#ifdef CONFIG_SMP

static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,

					 struct cpuidle_driver *drv,

					 int index)

{

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);



	cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);



	tegra20_cpu_clear_resettable();



	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);



	return true;

}

#else

static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,

						struct cpuidle_driver *drv,

						int index)

{

	return true;

}

#endif



static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,

				    struct cpuidle_driver *drv,

				    int index)

{

	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;

	bool entered_lp2 = false;



	if (tegra_pending_sgi())

		ACCESS_ONCE(abort_flag) = true;



	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);



	if (abort_flag) {

		cpuidle_coupled_parallel_barrier(dev, &abort_barrier);

		abort_flag = false;	/* clean flag for next coming */

		return -EINTR;

	}



	local_fiq_disable();



	tegra_set_cpu_in_lp2(cpu);

	cpu_pm_enter();



	if (cpu == 0)

		entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);

	else

		entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);



	cpu_pm_exit();

	tegra_clear_cpu_in_lp2(cpu);



	local_fiq_enable();



	smp_rmb();



	return entered_lp2 ? index : 0;

}

#endif



int __init tegra20_cpuidle_init(void)

{

	int ret;
@@ -44,6 +222,14 @@ int __init tegra20_cpuidle_init(void) 
	struct cpuidle_device *dev;

	struct cpuidle_driver *drv = &tegra_idle_driver;



#ifdef CONFIG_PM_SLEEP

	tegra_tear_down_cpu = tegra20_tear_down_cpu;

#endif



	drv->state_count = ARRAY_SIZE(tegra_idle_states);

	memcpy(drv->states, tegra_idle_states,

			drv->state_count * sizeof(drv->states[0]));



	ret = cpuidle_register_driver(&tegra_idle_driver);

	if (ret) {

		pr_err("CPUidle driver registration failed\n");
@@ -53,6 +239,9 @@ int __init tegra20_cpuidle_init(void) 
	for_each_possible_cpu(cpu) {

		dev = &per_cpu(tegra_idle_device, cpu);

		dev->cpu = cpu;

#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED

		dev->coupled_cpus = *cpu_possible_mask;

#endif



		dev->state_count = drv->state_count;

		ret = cpuidle_register_device(dev);

arch/arm/mach-tegra/flowctrl.c

+33 −5
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include "flowctrl.h"

#include "iomap.h"

#include "fuse.h"



static u8 flowctrl_offset_halt_cpu[] = {

	FLOW_CTRL_HALT_CPU0_EVENTS,
@@ -75,11 +76,26 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid) 
	int i;



	reg = flowctrl_read_cpu_csr(cpuid);

	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;	/* clear wfe bitmap */

	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;	/* clear wfi bitmap */

	switch (tegra_chip_id) {

	case TEGRA20:

		/* clear wfe bitmap */

		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;

		/* clear wfi bitmap */

		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;

		/* pwr gating on wfe */

		reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;

		break;

	case TEGRA30:

		/* clear wfe bitmap */

		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;

		/* clear wfi bitmap */

		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;

		/* pwr gating on wfi */

		reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;

		break;

	}

	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr flag */

	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event flag */

	reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;	/* pwr gating on wfi */

	reg |= FLOW_CTRL_CSR_ENABLE;			/* pwr gating */

	flowctrl_write_cpu_csr(cpuid, reg);
@@ -99,8 +115,20 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) 


	/* Disable powergating via flow controller for CPU0 */

	reg = flowctrl_read_cpu_csr(cpuid);

	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;	/* clear wfe bitmap */

	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;	/* clear wfi bitmap */

	switch (tegra_chip_id) {

	case TEGRA20:

		/* clear wfe bitmap */

		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;

		/* clear wfi bitmap */

		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;

		break;

	case TEGRA30:

		/* clear wfe bitmap */

		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;

		/* clear wfi bitmap */

		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;

		break;

	}

	reg &= ~FLOW_CTRL_CSR_ENABLE;			/* clear enable */

	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr */

	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event */

arch/arm/mach-tegra/flowctrl.h

+4 −0
Original line number Diff line number Diff line
@@ -34,6 +34,10 @@ 
#define FLOW_CTRL_HALT_CPU1_EVENTS	0x14

#define FLOW_CTRL_CPU1_CSR		0x18



#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0		(1 << 4)

#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP	(3 << 4)

#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP	0



#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0		(1 << 8)

#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP	(0xF << 4)

#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP	(0xF << 8)

arch/arm/mach-tegra/irq.c

+15 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ 


#define FIRST_LEGACY_IRQ 32



#define SGI_MASK 0xFFFF



static int num_ictlrs;



static void __iomem *ictlr_reg_base[] = {
@@ -54,6 +56,19 @@ static void __iomem *ictlr_reg_base[] = { 
	IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),

};



bool tegra_pending_sgi(void)

{

	u32 pending_set;

	void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);



	pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET);



	if (pending_set & SGI_MASK)

		return true;



	return false;

}



static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)

{

	void __iomem *base;