Commit e568006b authored Jun 17, 2016 by Aneesh Kumar K.V Committed by Michael Ellerman Jun 17, 2016

powerpc/mm/hash: Don't add memory coherence if cache inhibited is set



H_ENTER hcall handling in qemu had assumptions that a cache inhibited
hpte entry won't have memory conference set. Also older kernel
mentioned that some version of pHyp required this (the code removed
by the below commit says:

    /* Make pHyp happy */
    if ((rflags & _PAGE_NO_CACHE) && !(rflags & _PAGE_WRITETHRU))
            hpte_r &= ~HPTE_R_M;

But with older kernel we had some inconsistent memory conherence
mapping. We always enabled memory conherence in the page fault path and
removed memory conherence is _PAGE_NO_CACHE was set when we mapped the
page via htab_bolt_mapping. The commit mentioned below tried to
consolidate that by always enabling memory conherence. But as mentioned
above that breaks Qemu H_ENTER handling.

This patch update this such that we enable memory conherence only if
cache inhibited is not set and bring fault handling, lpar and bolt
mapping in sync.

Fixes: commit 30bda41a("powerpc/mm: Drop WIMG in favour of new constant")
Reported-by: Darrick J. Wong <darrick.wong@oracle.com>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent 8550e2fa

arch/powerpc/mm/hash_utils_64.c

+9 −5

Original line number	Diff line number	Diff line
		@@ -201,9 +201,8 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags)
		/*
		* We can't allow hardware to update hpte bits. Hence always
		* set 'R' bit and set 'C' if it is a write fault
		* Memory coherence is always enabled
		*/
		rflags \|= HPTE_R_R \| HPTE_R_M;
		rflags \|= HPTE_R_R;

		if (pteflags & _PAGE_DIRTY)
		rflags \|= HPTE_R_C;
		@@ -213,10 +212,15 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags)

		if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
		rflags \|= HPTE_R_I;
		if ((pteflags & _PAGE_CACHE_CTL ) == _PAGE_NON_IDEMPOTENT)
		else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
		rflags \|= (HPTE_R_I \| HPTE_R_G);
		if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
		rflags \|= (HPTE_R_I \| HPTE_R_W);
		else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
		rflags \|= (HPTE_R_W \| HPTE_R_I \| HPTE_R_M);
		else
		/*
		* Add memory coherence if cache inhibited is not set
		*/
		rflags \|= HPTE_R_M;

		return rflags;
		}