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Commit 8550e2fa authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
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powerpc/mm/hash: Use the correct PPP mask when updating HPTE 



With commit e58e87ad "powerpc/mm: Update _PAGE_KERNEL_RO" we now
use all the three PPP bits. The top bit is now used to have a PPP value
of 0b110 which will be mapped to kernel read only. When updating the
hpte entry use right mask such that we update the 63rd bit (top 'P' bit)
too.

Prior to e58e87ad we didn't support KERNEL_RO at all (it was ==
KERNEL_RW), so this isn't a regression as such.

Fixes: e58e87ad ("powerpc/mm: Update _PAGE_KERNEL_RO")
Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent a145abf1

arch/powerpc/include/asm/book3s/64/mmu-hash.h

+1 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ 
#define HPTE_R_RPN_SHIFT	12

#define HPTE_R_RPN		ASM_CONST(0x0ffffffffffff000)

#define HPTE_R_PP		ASM_CONST(0x0000000000000003)

#define HPTE_R_PPP		ASM_CONST(0x8000000000000003)

#define HPTE_R_N		ASM_CONST(0x0000000000000004)

#define HPTE_R_G		ASM_CONST(0x0000000000000008)

#define HPTE_R_M		ASM_CONST(0x0000000000000010)

arch/powerpc/mm/hash_native_64.c

+4 −4
Original line number Diff line number Diff line
@@ -316,8 +316,8 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp, 
			DBG_LOW(" -> hit\n");

			/* Update the HPTE */

			hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &

						~(HPTE_R_PP | HPTE_R_N)) |

					       (newpp & (HPTE_R_PP | HPTE_R_N |

						~(HPTE_R_PPP | HPTE_R_N)) |

					       (newpp & (HPTE_R_PPP | HPTE_R_N |

							 HPTE_R_C)));

		}

		native_unlock_hpte(hptep);
@@ -385,8 +385,8 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea, 


	/* Update the HPTE */

	hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &

			~(HPTE_R_PP | HPTE_R_N)) |

		(newpp & (HPTE_R_PP | HPTE_R_N)));

				~(HPTE_R_PPP | HPTE_R_N)) |

			       (newpp & (HPTE_R_PPP | HPTE_R_N)));

	/*

	 * Ensure it is out of the tlb too. Bolted entries base and

	 * actual page size will be same.