Loading drivers/dca/dca-core.c +2 −1 Original line number Diff line number Diff line Loading @@ -321,7 +321,8 @@ EXPORT_SYMBOL_GPL(dca_get_tag); * @ops - pointer to struct of dca operation function pointers * @priv_size - size of extra mem to be added for provider's needs */ struct dca_provider *alloc_dca_provider(struct dca_ops *ops, int priv_size) struct dca_provider *alloc_dca_provider(const struct dca_ops *ops, int priv_size) { struct dca_provider *dca; int alloc_size; Loading drivers/dma/ioat/dca.c +1 −1 Original line number Diff line number Diff line Loading @@ -224,7 +224,7 @@ static u8 ioat_dca_get_tag(struct dca_provider *dca, return tag; } static struct dca_ops ioat_dca_ops = { static const struct dca_ops ioat_dca_ops = { .add_requester = ioat_dca_add_requester, .remove_requester = ioat_dca_remove_requester, .get_tag = ioat_dca_get_tag, Loading drivers/dma/ioat/dma.h +1 −33 Original line number Diff line number Diff line Loading @@ -235,43 +235,11 @@ ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index) return ioat_dma->idx[index]; } static inline u64 ioat_chansts_32(struct ioatdma_chan *ioat_chan) { u8 ver = ioat_chan->ioat_dma->version; u64 status; u32 status_lo; /* We need to read the low address first as this causes the * chipset to latch the upper bits for the subsequent read */ status_lo = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); status = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); status <<= 32; status |= status_lo; return status; } #if BITS_PER_LONG == 64 static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan) { u8 ver = ioat_chan->ioat_dma->version; u64 status; /* With IOAT v3.3 the status register is 64bit. */ if (ver >= IOAT_VER_3_3) status = readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); else status = ioat_chansts_32(ioat_chan); return status; return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET); } #else #define ioat_chansts ioat_chansts_32 #endif static inline u64 ioat_chansts_to_addr(u64 status) { return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; Loading drivers/dma/ioat/registers.h +3 −13 Original line number Diff line number Diff line Loading @@ -99,19 +99,9 @@ #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ #define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */ #define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ #define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET) #define IOAT1_CHANSTS_OFFSET_LOW 0x04 #define IOAT2_CHANSTS_OFFSET_LOW 0x08 #define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW) #define IOAT1_CHANSTS_OFFSET_HIGH 0x08 #define IOAT2_CHANSTS_OFFSET_HIGH 0x0C #define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH) /* IOAT1 define left for i7300_idle driver to not fail compiling */ #define IOAT1_CHANSTS_OFFSET 0x04 #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) #define IOAT_CHANSTS_SOFT_ERR 0x10ULL #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL Loading include/linux/dca.h +3 −2 Original line number Diff line number Diff line Loading @@ -34,7 +34,7 @@ void dca_unregister_notify(struct notifier_block *nb); struct dca_provider { struct list_head node; struct dca_ops *ops; const struct dca_ops *ops; struct device *cd; int id; }; Loading @@ -53,7 +53,8 @@ struct dca_ops { int (*dev_managed) (struct dca_provider *, struct device *); }; struct dca_provider *alloc_dca_provider(struct dca_ops *ops, int priv_size); struct dca_provider *alloc_dca_provider(const struct dca_ops *ops, int priv_size); void free_dca_provider(struct dca_provider *dca); int register_dca_provider(struct dca_provider *dca, struct device *dev); void unregister_dca_provider(struct dca_provider *dca, struct device *dev); Loading Loading
drivers/dca/dca-core.c +2 −1 Original line number Diff line number Diff line Loading @@ -321,7 +321,8 @@ EXPORT_SYMBOL_GPL(dca_get_tag); * @ops - pointer to struct of dca operation function pointers * @priv_size - size of extra mem to be added for provider's needs */ struct dca_provider *alloc_dca_provider(struct dca_ops *ops, int priv_size) struct dca_provider *alloc_dca_provider(const struct dca_ops *ops, int priv_size) { struct dca_provider *dca; int alloc_size; Loading
drivers/dma/ioat/dca.c +1 −1 Original line number Diff line number Diff line Loading @@ -224,7 +224,7 @@ static u8 ioat_dca_get_tag(struct dca_provider *dca, return tag; } static struct dca_ops ioat_dca_ops = { static const struct dca_ops ioat_dca_ops = { .add_requester = ioat_dca_add_requester, .remove_requester = ioat_dca_remove_requester, .get_tag = ioat_dca_get_tag, Loading
drivers/dma/ioat/dma.h +1 −33 Original line number Diff line number Diff line Loading @@ -235,43 +235,11 @@ ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index) return ioat_dma->idx[index]; } static inline u64 ioat_chansts_32(struct ioatdma_chan *ioat_chan) { u8 ver = ioat_chan->ioat_dma->version; u64 status; u32 status_lo; /* We need to read the low address first as this causes the * chipset to latch the upper bits for the subsequent read */ status_lo = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); status = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); status <<= 32; status |= status_lo; return status; } #if BITS_PER_LONG == 64 static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan) { u8 ver = ioat_chan->ioat_dma->version; u64 status; /* With IOAT v3.3 the status register is 64bit. */ if (ver >= IOAT_VER_3_3) status = readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); else status = ioat_chansts_32(ioat_chan); return status; return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET); } #else #define ioat_chansts ioat_chansts_32 #endif static inline u64 ioat_chansts_to_addr(u64 status) { return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; Loading
drivers/dma/ioat/registers.h +3 −13 Original line number Diff line number Diff line Loading @@ -99,19 +99,9 @@ #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ #define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */ #define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ #define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET) #define IOAT1_CHANSTS_OFFSET_LOW 0x04 #define IOAT2_CHANSTS_OFFSET_LOW 0x08 #define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW) #define IOAT1_CHANSTS_OFFSET_HIGH 0x08 #define IOAT2_CHANSTS_OFFSET_HIGH 0x0C #define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH) /* IOAT1 define left for i7300_idle driver to not fail compiling */ #define IOAT1_CHANSTS_OFFSET 0x04 #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) #define IOAT_CHANSTS_SOFT_ERR 0x10ULL #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL Loading
include/linux/dca.h +3 −2 Original line number Diff line number Diff line Loading @@ -34,7 +34,7 @@ void dca_unregister_notify(struct notifier_block *nb); struct dca_provider { struct list_head node; struct dca_ops *ops; const struct dca_ops *ops; struct device *cd; int id; }; Loading @@ -53,7 +53,8 @@ struct dca_ops { int (*dev_managed) (struct dca_provider *, struct device *); }; struct dca_provider *alloc_dca_provider(struct dca_ops *ops, int priv_size); struct dca_provider *alloc_dca_provider(const struct dca_ops *ops, int priv_size); void free_dca_provider(struct dca_provider *dca); int register_dca_provider(struct dca_provider *dca, struct device *dev); void unregister_dca_provider(struct dca_provider *dca, struct device *dev); Loading